W83627UHG Nuvoton Technology Corporation of America, W83627UHG Datasheet - Page 137

• Manufacturer Part Number: W83627UHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627UHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V, 5V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.3.5
This mode is defined only for the forward direction. Bytes written or DMAed to this FIFO are
transmitted by a hardware handshake to the peripheral using the standard parallel port protocol.
Transfers to the FIFO are byte-aligned.
11.3.6
When the direction bit is 0, bytes written or DMAed to this FIFO are transmitted by a hardware
handshake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO are byte-
aligned.
When the direction bit is 1, data bytes from the peripheral are read via automatic hardware handshake
from ECP into this FIFO. Reads or DMAs from the FIFO return bytes of ECP data to the system.
11.3.7
Data bytes may be read, written, or DMAed to or from the system to this FIFO in any direction. Data in
the tFIFO is not transmitted to the parallel port lines. However, data in the tFIFO may be displayed on
the parallel port data lines.
11.3.8
This register is a read-only register. When it is read, 10H is returned. This indicates that this is an 8-bit
implementation.
BIT
7-6
5
4
3
2
1
0
These two bits are always read as logical 1 and cannot be written.
Director. If the mode is 000 or 010, this bit has no effect and the direction is always out.
In other modes,
0: The parallel port is in the output mode.
1: The parallel port is in the input mode.
ackInEn (Interrupt Request Enable). When this bit is set to logical 1, it enables interrupt
requests from the parallel port to the CPU on the low-to-high transition on ACK#.
SelectIn. This bit is inverted and output to the SLIN# output.
0: The printer is not selected.
1: The printer is selected.
nInit. This bit is output to the INIT# output.
Autofd. This bit is inverted and output to the AFD# output.
Strobe. This bit is inverted and output to the STB# output.
CFIFO (Parallel Port Data FIFO) Mode = 010
ECPDFIFO (ECP Data FIFO) Mode = 011
TFIFO (Test FIFO Mode) Mode = 110
CNFGA (Configuration Register A) Mode = 111
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DESCRIPTION
W83627UHG