PI7C7300DNAE Pericom Semiconductor, PI7C7300DNAE Datasheet - Page 62

• Manufacturer Part Number: PI7C7300DNAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300DNAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 660 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pericom Semiconductor
Table 7-6 ASSERTION OF S_PERR#
Table 7-7 ASSERTION OF P_SERR# FOR DATA PARITY ERRORS
X = don’t care
2
the initiator (primary) bus.
Table 7-7 shows assertion of P_SERR#. This signal is set under the following conditions:
X = don’t care
2
3
The parity error was detected on the target (secondary) bus but not on
The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
The parity error was detected on the target (primary) bus but not on the initiator (secondary) bus.
S_PERR#
1 (de-asserted)
0 (asserted)
1
1
1
1
1
0
1
1
0
0
P_SERR#
1 (de-asserted)
1
1
1
1
0
0
1
1
1
1
1
2
2
3
(asserted)
PI7C7300D has detected P_PERR# asserted on an upstream posted write transaction
or S_PERR# asserted on a downstream posted write transaction.
PI7C7300D did not detect the parity error as a target of the posted write transaction.
The parity error response bit on the command register and the parity error response
bit on the bridge control register must both be set.
The SERR# enable bit must be set in the command register.
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Page 62 of 107
Direction
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Direction
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
3-PORT PCI-TO-PCI BRIDGE
Bus Where Error
Was Detected
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Bus Where Error
Was Detected
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
November 2005 - Revision 1.01
Primary/
Secondary Parity
Error Response
Bits
x / x
x / 1
x / x
x / x
x / x
x / x
x / x
x / 1
x / x
x / x
1 / 1
x / 1
Primary /
Secondary Parity
Error Response
Bits
x / x
x / x
x / x
x / x
x / x
1 / 1
1 / 1
x / x
x / x
x / x
x / x
x / x
PI7C7300D