PI7C7300DNAE Pericom Semiconductor, PI7C7300DNAE Datasheet - Page 7

• Manufacturer Part Number: PI7C7300DNAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300DNAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 660 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13
14
Pericom Semiconductor
13.1
13.2
14.1
14.1.1
14.1.2
14.1.3
14.1.4
14.1.5
14.1.6
14.1.7
14.1.8
14.1.9
14.1.10
14.1.11
14.1.12
14.1.13
14.1.14
14.1.15
14.1.16
14.1.17
14.1.18
14.1.19
14.1.20
14.1.21
28h
14.1.22
2Ch
14.1.23
14.1.24
14.1.25
14.1.26
14.1.27
14.1.28
14.1.29
14.1.30
14.1.31
14.1.32
14.1.33
54h
14.1.34
58h
14.1.35
14.1.36
14.1.37
14.1.38
14.1.39
14.1.40
14.1.41
SUPPORTED COMMANDS ...................................................................................................... 72
CONFIGURATION REGISTERS ............................................................................................. 73
PRIMARY INTERFACE ........................................................................................................... 72
SECONDARY INTERFACE..................................................................................................... 73
CONFIGURATION REGISTER 1 AND 2................................................................................ 75
VENDOR ID REGISTER – OFFSET 00h........................................................................... 75
DEVICE ID REGISTER – OFFSET 00h ............................................................................ 76
COMMAND REGISTER – OFFSET 04h ........................................................................... 76
STATUS REGISTER – OFFSET 04h.................................................................................. 77
REVISION ID REGISTER – OFFSET 08h......................................................................... 78
CLASS CODE REGISTER – OFFEST 08h ........................................................................ 78
CACHE LINE SIZE REGISTER – OFFSET 0Ch ............................................................... 78
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch................................................ 78
HEADER TYPE REGISTER – OFFSET 0Ch ..................................................................... 79
PRIMARY BUS NUMBER REGISTER – OFFSET 18h ................................................. 79
SECONDARY (S1 or S2) BUS NUMBER REGISTER – OFFSET 18h .......................... 79
SUBORDINATE (S1 or S2) BUS NUMBER REGISTER – OFFSET 18h ...................... 79
SECONDARY LATENCY TIMER REGISTER – OFFSET 18h ...................................... 79
I/O BASE REGISTER – OFFSET 1Ch ........................................................................... 80
I/O LIMIT REGISTER – OFFSET 1Ch .......................................................................... 80
SECONDARY STATUS REGISTER – OFFSET 1Ch...................................................... 80
MEMORY BASE REGISTER – OFFSET 20h................................................................. 81
MEMORY LIMIT REGISTER – OFFSET 20h................................................................ 81
PREFETCHABLE MEMORY BASE REGISTER – OFFSET 24h .................................. 82
PREFETCHABLE MEMORY LIMIT REGISTER – OFFSET 24h ................................. 82
PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER – OFFSET
PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER – OFFSET
I/O BASE ADDRESS UPPER 16-BITS REGISTER – Offset 30h................................... 83
I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h............................. 83
ECP POINTER REGISTER – OFFSET 34h................................................................... 83
BRIDGE CONTROL REGISTER – OFFSET 3Ch.......................................................... 83
DIAGNOSTIC / CHIP CONTROL REGISTER – OFFSET 40h ..................................... 85
ARBITER CONTROL REGISTER – OFFSET 40h......................................................... 86
UPSTREAM MEMORY CONTROL REGISTER – OFFSET 48h................................... 86
HOT SWAP SWITCH TIME SLOT REGISTER – OFFSET 4Ch.................................... 86
UPSTREAM (S1 or S2 to P) MEMORY BASE REGISTER – OFFSET 50h................... 87
UPSTREAM (S1 or S2 to P) MEMORY LIMIT REGISTER – OFFSET 50h.................. 87
UPSTREAM (S1 or S2 to P) MEMORY BASE UPPER 32-BITS REGISTER – OFFSET
UPSTREAM (S1 or S2 to P) MEMORY LIMIT UPPER 32 BITS REGISTER – OFFSET
P_SERR# EVENT DISABLE REGISTER – OFFSET 64h .............................................. 88
SECONDARY CLOCK CONTROL REGISTER – OFFSET 68h .................................... 89
PORT OPTION REGISTER – OFFSET 74h .................................................................. 89
MASTER TIMEOUT COUNTER REGISTER – OFFSET 74h ....................................... 91
RETRY COUNTER REGISTER – OFFSET 78h............................................................. 91
SAMPLING TIMER REGISTER – OFFSET 7Ch........................................................... 91
SECONDARY SUCCESSFUL I/O READ COUNTER REGISTER – OFFSET 80h ....... 91
........................................................................................................................................ 82
........................................................................................................................................ 82
........................................................................................................................................ 87
........................................................................................................................................ 88
Page 7 of 107
3-PORT PCI-TO-PCI BRIDGE
November 2005 - Revision 1.01
PI7C7300D