MT16HTF25664HZ-667H1 Micron Technology Inc, MT16HTF25664HZ-667H1 Datasheet - Page 14

• Manufacturer Part Number: MT16HTF25664HZ-667H1
• Description: MODULE DDR2 SDRAM 2GB 200SODIMM
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT16HTF25664HZ-667H1

• Memory Type: DDR2 SDRAM
• Memory Size: 2GB
• Speed: 667MT/s
• Features: -
• Package / Case: 200-SODIMM
• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 200SODIMM
• Device Core Size: 64b
• Organization: 256Mx64
• Total Density: 2GByte
• Chip Density: 128Mb
• Access Time (max): 900ns
• Package Type: SODIMM
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 1.136A
• Number Of Elements: 16
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 200
• Mounting: Socket
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 12: DDR2 I
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) com-
ponent data sheet
Table 13: DDR2 I
Values shown for MT47H256M8 DDR2 SDRAM only and are computed from values specified in the 2Gb (256 Meg x 8) com-
ponent data sheet
PDF: 09005aef8339ef97
htf16c128_256_512x64hz.pdf - Rev. C 9/10 EN
Parameter
Active standby current: All device banks open;
MAX (I
er
Operating burst write current: All device banks open; Continuous burst writes;
BL = 4, CL = CL (I
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switch-
ing; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst read,
I
t
puts are switching; Data bus inputs are switching
Burst refresh current:
terval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address
bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving reads;
I
=
valid commands; Address bus inputs are stable during deselects; Data bus inputs
are switching
Parameter
Operating one bank active-precharge current:
t
bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
CL (I
(I
switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
LOW; Other control and address bus inputs are stable; Data bus inputs are floating
OUT
RP =
OUT
RAS =
DD
t
RC (I
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are
DD
= 0mA; BL = 4, CL = CL (I
= 0mA; BL = 4, CL = CL (I
t
RP (I
), AL = 0;
DD
DD
t
RAS MIN (I
),
),
DD
t
t
RP =
RRD =
); CKE is HIGH, S# is HIGH between valid commands; Address bus in-
t
DD
CK =
t
RP (I
DD
t
), AL = 0;
RRD (I
DD
DD
); CKE is HIGH, S# is HIGH between valid commands; Address
DD
Notes:
t
CK (I
Specifications and Conditions – 2GB (Die Revision H) (Continued)
Specifications and Conditions – 4GB (Die Revision A)
t
); CKE is HIGH, S# is HIGH between valid commands; Oth-
CK =
DD
DD
),
t
DD
DD
CK =
t
),
t
RCD =
CK (I
1. Value calculated as one module rank in this operating condition; all other module ranks
2. Value calculated reflects all module ranks in this operating condition.
), AL = 0;
), AL =
t
RC =
in I
t
CK (I
DD
DD4W
t
DD2P
t
); REFRESH command at every
RCD (I
RC (I
t
RCD (I
DD
t
1GB, 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM
CK =
),
(CKE LOW) mode.
DD
t
DD
RAS =
),
DD
); CKE is HIGH, S# is HIGH between
t
t
CK (I
) - 1 ×
RAS =
t
CK =
t
t
RAS MAX (I
DD
CK =
t
t
),
CK (I
RAS MIN (I
t
t
CK (I
RAS =
t
CK (I
t
OUT
CK =
DD
14
DD
);
= 0mA; BL = 4, CL =
DD
DD
t
t
),
RAS MAX (I
CK =
t
CK (I
),
DD
),
t
RAS =
t
t
RC =
),
RP =
t
RFC (I
t
DD
t
CK (I
RCD =
Micron Technology, Inc. reserves the right to change products or specifications without notice.
); CKE is
t
t
t
RC (I
RAS
RP (I
DD
DD
DD
) in-
),
t
RCD
),
DD
DD
t
RC
),
);
Symbol
Symbol
I
I
I
DD4W
I
I
I
DD3N
DD4R
I
DD5
DD6
DD7
I
I
DD2P
DD0
DD1
2
2
1
1
2
1
1
1
2
© 2008 Micron Technology, Inc. All rights reserved.
-1GA
1296
1256
1496
2056
IDD Specifications
-1GA
640
112
TBD
TBD
TBD
-80E/
-80E/
-800
1056
1016
1216 1176
1736 1536
-800 -667 Units
1016
1416 1256
528
112
192
-667 Units
480
976
936
112
896
192
mA
mA
mA
mA
mA
mA
mA
mA
mA