MT18HTF25672FDZ-80EH1D6 Micron Technology Inc, MT18HTF25672FDZ-80EH1D6 Datasheet - Page 11

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MT18HTF25672FDZ-80EH1D6

Manufacturer Part Number
MT18HTF25672FDZ-80EH1D6
Description
MODULE DDR2 SDRAM 2GB 240FBDIMM
Manufacturer
Micron Technology Inc
Series
-r
Datasheet

Specifications of MT18HTF25672FDZ-80EH1D6

Memory Type
DDR2 SDRAM
Memory Size
2GB
Speed
800MT/s
Features
-
Package / Case
240-FBDIMM
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Table 12: Serial Presence-Detect EEPROM DC Operating Conditions
Table 13: Serial Presence-Detect EEPROM AC Operating Conditions
Serial Presence-Detect Data
PDF: 09005aef83d4d75e
htf18c128_256x72fdz.pdf - Rev. B 07/10 EN
Parameter/Condition
EEPROM and AMB supply voltage
Input high voltage: Logic 1; all inputs
Input low voltage: Logic 0; all inputs
Output low voltage: I
Input leakage current: V
Output leakage current: V
Standby current
Power supply current, READ: SCL clock frequency = 100 kHz
Power supply current, WRITE: SCL clock frequency = 100 kHz
Parameter/Condition
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
OUT
Notes:
IN
= 3mA
OUT
= GND to V
For the latest serial presence-detect data, refer to Micron's SPD page:
SPD.
= GND to V
1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1
2. This parameter is sampled.
3. For a restart condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
and the falling or rising edge of SDA.
write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the
WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-
up resistance, and the EEPROM does not respond to its slave address.
DD
DD
1GB, 2GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM
11
Symbol
Symbol
t
t
t
t
t
HD:DAT
V
HD:STA
SU:DAT
SU:STO
SU:STA
t
t
t
I
HIGH
t
DDSPD
LOW
f
WRC
V
I
t
t
V
CCW
BUF
V
I
I
CCR
SCL
AA
DH
I
t
LO
t
SB
LI
t
OL
IH
R
F
IL
I
t
Micron Technology, Inc. reserves the right to change products or specifications without notice.
WRC) is the time from a valid stop condition of a
Serial Presence-Detect EEPROM
V
Min
DDSPD
200
100
0.2
1.3
0.6
0.6
1.3
0.6
0.6
0
Min
–0.6
0.10
0.05
1.6
0.4
3
2
× 0.7
Max
300
400
0.9
0.3
50
10
© 2009 Micron Technology, Inc. All rights reserved.
V
V
DDSPD
DDSPD
Max
3.6
0.4
3
3
4
1
3
www.micron.com/
Units
kHz
+ 0.5
× 0.3
ms
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
ns
µs
µs
Notes
Units
mA
mA
µA
µA
µA
V
V
V
V
1
2
2
3
4

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