SI4731-D60-GU Silicon Laboratories Inc, SI4731-D60-GU Datasheet - Page 24

• Manufacturer Part Number: SI4731-D60-GU
• Description: IC RADIO RX AM/FM/AUX 24SSOP
• Manufacturer: Silicon Laboratories Inc
• Series: -r

Specifications of SI4731-D60-GU

• Frequency: 153kHz ~ 279kHz, 520kHz ~ 1.71MHz, 2.3MHz ~ 26.1MHz, 64MHz ~ 108MHz
• Sensitivity: -
• Data Rate - Maximum: -
• Modulation Or Protocol: AM, FM, SW-LW
• Applications: General Purpose
• Current - Receiving: 18.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: -
• Antenna Connector: PCB, Surface Mount
• Features: -
• Voltage - Supply: 2 V ~ 5.5 V
• Operating Temperature: -20°C ~ 85°C
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Si4730/31/34/35-D60
4.6. LW Receiver
The Si4734/35 supports the long wave (LW) band from
153 to 279 kHz. The highly integrated Si4734/35 offers
continuous
components and no factory adjustments. The Si4734/35
also offers adjustable channel step sizes in 1 kHz
increments, adjustable channel bandwidth settings,
advanced seek algorithm, and soft mute.
The Si4734/35 uses a separate ferrite bar antenna to
capture long wave signals.
4.7. Stereo Audio AUXIN ADC
The Si473x-D60 stereo audio AUXIN ADC can be
multiplexed between low-IF input for radio operation
and analog audio input for high fidelity data conversion
at 32, 44.1, or 48 kHz sample rate. When operated in
ADC-mode, the Si473x-D60 supports I
output only (no analog output) while enabling the analog
inputs and the stereo ADC.
4.8. Digital Audio Interface
The digital audio interface operates in slave mode and
supports a variety of MSB-first audio data formats
including I
three pins: digital data input (DIN), digital frame
synchronization
synchronization input clock (DCLK). The Si4731/35
supports a number of industry-standard sampling rates
including 32, 44.1, and 48 kHz. The digital audio
interface enables low-power operation by eliminating
the need for redundant DACs and ADCs on the audio
baseband processor.
4.8.1. Audio Data Formats
The digital audio interface operates in slave mode and
supports three different audio data formats:



In I
second rising edge of DCLK following each DFS
transition. The remaining bits of the word are sent in
order, down to the LSB. The left channel is transferred
first when the DFS is low, and the right channel is
transferred when the DFS is high.
In left-justified mode, by default the MSB is captured on
the first rising edge of DCLK following each DFS
transition. The remaining bits of the word are sent in
order, down to the LSB. The left channel is transferred
first when the DFS is high, and the right channel is
transferred when the DFS is low.
24
I
Left-Justified
DSP Mode
2
2
S mode, by default the MSB is captured on the
S
(Si4731/35 Only)
2
S and left-justified modes. The interface has
digital
input
tuning
(DFS),
with
and
minimal
2
S digital audio
a
digital
discrete
Rev. 1.0
bit
In DSP mode, the DFS becomes a pulse with a width of
1DCLK period. The left channel is transferred first,
followed right away by the right channel. There are two
options in transferring the digital audio data in DSP
mode: the MSB of the left channel can be transferred on
the first rising edge of DCLK following the DFS pulse or
on the second rising edge.
In all audio formats, depending on the word size, DCLK
frequency, and sample rates, there may be unused
DCLK cycles after the LSB of each word before the next
DFS transition and MSB of the next word. In addition, if
preferred, the user can configure the MSB to be
captured on the falling edge of DCLK via properties.
The number of audio bits can be configured for 8, 16,
20, or 24 bits.
4.8.2. Audio Sample Rates
The device supports a number of industry-standard
sampling rates including 32, 44.1, and 48 kHz. The
digital audio interface enables low-power operation by
eliminating the need for redundant DACs on the audio
baseband processor.