LFXP20E-4F484C Lattice, LFXP20E-4F484C Datasheet - Page 225

• Manufacturer Part Number: LFXP20E-4F484C
• Description: IC FPGA 19.7KLUTS 340I/O 484-BGA
• Manufacturer: Lattice

Specifications of LFXP20E-4F484C

• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant

Lattice Semiconductor
The DLL Lock Detect circuit has two modes of operation controlled by the LOCK_SENSITIVITY bit, which selects
more or less sensitivity to jitter. If this DLL is operated at or above 150 MHz, it is recommended that the
LOCK_SENSITIVITY bit be programmed “HIGH” (more sensitive). For operation running at or under 100 MHz it is
recommended that the bit be programmed “LOW” (more tolerant). For 133 MHz, the LOCK_SENSITIVITY bit can
go either way.
DQSBUF
This primitive implements the DQS Delay and the DQS transition detector logic. Figure 10-6 shows the DQSBUFB
function. The preamble detect signal is also generated within this primitive.
Figure 10-6. DQSBUFB Function
Figure 10-7 shows the primitive symbol and its ports. DQSI is the DQS signal from the memory. PRMBDET is the
preamble detect signal that is generated from the DQSI input. READ and CLK are user interface signals coming
from the FPGA logic. The DQSDLL block sends digital control line DQSDEL to this block. The DQS is delayed
based on this input from the DQSDLL. DQSO is the delayed DQS and is connected to the clock input of the first set
of DDR registers.
Figure 10-7. DQSBUFB Symbol
Table 10-5 provides a description of the I/O ports associated with the DQSBUFB primitive.
READ
DQSI
CLK
V
(DV ~ 170mV)
REF
V
REF
- DV
+
-
+
-
PRMBDET
DQSI
CLK
READ
DQSDEL
DQSBUFB
DQSBUFB
10-6
DDRCLKPOL
TRANSITION
PRMBDET
DQSDEL
DETECT
DQS
DQSO
DQSC
DQSDEL
LatticeECP/EC and LatticeXP
DQSC
PRMBDET
DDRCLKPOL
DQSO
DDR Usage Guide