LFXP20E-4F484C Lattice, LFXP20E-4F484C Datasheet - Page 6

• Manufacturer Part Number: LFXP20E-4F484C
• Description: IC FPGA 19.7KLUTS 340I/O 484-BGA
• Manufacturer: Lattice

Specifications of LFXP20E-4F484C

• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant

Lattice Semiconductor
LatticeECP/EC and LatticeXP sysCLOCK PLL Design and Usage Guide
Power Estimation and Management for LatticeECP/EC and LatticeXP Devices
Introduction ...................................................................................................................................................... 11-1
Features ........................................................................................................................................................... 11-1
Functional Description...................................................................................................................................... 11-1
LatticeECP/EC and LatticeXP PLL Primitive Definitions.................................................................................. 11-4
PLL Usage in IPexpress................................................................................................................................... 11-7
Equations for Generating Input and Output Frequency Ranges .................................................................... 11-10
Clock Distribution in LatticeECP/EC and LatticeXP ....................................................................................... 11-11
Clock Net Preferences ................................................................................................................................... 11-12
Dynamic Clock Selection (DCS) .................................................................................................................... 11-14
Other Design Considerations ......................................................................................................................... 11-17
DCS Usage with VHDL .................................................................................................................................. 11-18
Technical Support Assistance........................................................................................................................ 11-19
Revision History ............................................................................................................................................. 11-19
Appendix A. Clock Preferences ..................................................................................................................... 11-20
Introduction ...................................................................................................................................................... 12-1
Power Supply Sequencing and Hot Socketing................................................................................................. 12-1
Power Calculator Hardware Assumptions........................................................................................................ 12-1
Power Calculator.............................................................................................................................................. 12-1
PLL Divider and Delay Blocks................................................................................................................. 11-1
PLL Inputs and Outputs .......................................................................................................................... 11-2
PLL Attributes.......................................................................................................................................... 11-3
PLL Attributes Definitions........................................................................................................................ 11-4
Dynamic Delay Adjustment ..................................................................................................................... 11-6
Including sysCLOCK PLLs in a Design................................................................................................... 11-7
IPexpress Usage..................................................................................................................................... 11-7
EHXPLLB Example Projects ................................................................................................................... 11-9
f
f
Primary Clock Sources and Distribution................................................................................................ 11-11
Primary-Pure and Primary-DCS............................................................................................................ 11-12
Global Primary Clock and Quadrant Primary Clock .............................................................................. 11-12
Secondary Clock Sources and Distribution........................................................................................... 11-13
Limitations on Secondary Clock Availability.......................................................................................... 11-13
DCS Waveforms ................................................................................................................................... 11-15
Use of DCS with PLL ............................................................................................................................ 11-17
Jitter Considerations ............................................................................................................................. 11-17
Simulation Limitations ........................................................................................................................... 11-17
PCB Layout Recommendations for VCCPLL and GNDPLL if Separate Pins are Available ................. 11-18
DCS Usage with Verilog........................................................................................................................ 11-18
ASIC...................................................................................................................................................... 11-20
FREQUENCY........................................................................................................................................ 11-20
MAXSKEW............................................................................................................................................ 11-20
MULTICYCLE ....................................................................................................................................... 11-20
PERIOD ................................................................................................................................................ 11-20
PROHIBIT ............................................................................................................................................. 11-20
CLOCK_TO_OUT ................................................................................................................................. 11-20
INPUT_SETUP ..................................................................................................................................... 11-21
PLL_PHASE_BACK.............................................................................................................................. 11-21
Power Calculator Equations.................................................................................................................... 12-2
Starting the Power Calculator ................................................................................................................. 12-3
Starting a Power Calculator Project ........................................................................................................ 12-5
Power Calculator Main Window .............................................................................................................. 12-6
VCO
PFD
Constraint ...................................................................................................................................... 11-10
Constraint ..................................................................................................................................... 11-10
5
LatticeXP Family Handbook
Table of Contents