LFXP20E-4F484C Lattice, LFXP20E-4F484C Datasheet - Page 236

• Manufacturer Part Number: LFXP20E-4F484C
• Description: IC FPGA 19.7KLUTS 340I/O 484-BGA
• Manufacturer: Lattice

Specifications of LFXP20E-4F484C

• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant

Lattice Semiconductor
QDR II Interface
QDR II SRAM is a new memory technology defined by a number of leading memory vendors for high-performance
and high-bandwidth communication applications. QDR is a synchronous pipelined burst SRAM with two separate
unidirectional data buses dedicated for read and write operations running at double data rate. Both the QDR II read
and write interfaces use HSTL 1.8V I/O standard.
A QDR II memory controller can be easily implemented using the LatticeECP/EC and LatticeXP devices by taking
advantage of the DDR I/O registers. For LatticeECP/EC and LatticeXP devices, ODDRXB primitives are used on
the QDR outputs and PFU registers are used on the QDR inputs to implement the DDR interface. To see the details
of this implementation refer to Lattice reference design RD1019, QDR Memory Controller on the Lattice web site at
www.latticesemi.com.
FCRAM (Fast Cycle Random Access Memory) Interface
FCRAM is a DDR-type DRAM, which performs data output at both the rising and the falling edges of the clock.
FCRAM devices operate at a core voltage of 2.5V with SSTL Class II I/O. It has enhanced both the core and
peripheral logic of the SDRAM. In FCRAM the address and command signals are synchronized with the clock
input, and the data pins are synchronized with the DQS signal. Data output takes place at both the rising and falling
edges of the DQS. DQS is in phase with the clock input of the device. The DDR SDRAM and DDR FCRAM control-
ler will have different pin outs.
LatticeECP/EC and LatticeXP devices can implement an FCRAM interface using the dedicated DQS logic, input
DDR registers and output DDR registers as described in the Implementing Memory Interfaces section of this docu-
ment. Generation of address and control signals for FCRAM are different compared to the DDR SDRAM devices.
Please refer to the FCRAM data sheets to see detailed specifications. Toshiba, Inc. and Fujitsu, Inc. offer FCRAM
devices in 256Mb densities. They are available in x8 or x16 configurations.
Generic High Speed DDR Implementation
In addition to the DDR memory interface, users can use the I/O logic registers to implement a high speed DDR
interface. DDR data write operations can be implemented using the DDR output registers similar to the memory
interface implementation using the ODDRXB primitives.
On the input side, the read interface can be implemented using the core logic PFU registers. The PFU register next
to the I/O cells can be used to de-mux the DDR data to single data rate data. This method of implementing DDR
can run at 300 MHz when accompanied by proper preferences in the software. The HDL and the preferences to
implement this DDR interface are listed in Appendix D of this document.
Board Design Guidelines
The most common challenge associated with implementing DDR memory interfaces is the board design and lay-
out. Users must strictly follow the guidelines recommended by memory device vendors.
Some common recommendations include matching trace lengths of interface signals to avoid skew, proper DQ-
DQS signal grouping, proper termination of the SSTL2 I/O standard, proper VREF and VTT generation decoupling
and proper PCB routing.
• The DDR SDRAM interface supports the SSTL25 I/O standard, therefore the interface pins should be
• When implementing a DDR interface, the VREF1 of the bank is used to provide the reference voltage for the
• Appendix F shows DDR400 implementation results of the LatticeEC Advanced Evaluation Board.
assigned as SSTL25 I/O type.
interface pins.
10-17
LatticeECP/EC and LatticeXP
DDR Usage Guide