LFXP20E-4F484C Lattice, LFXP20E-4F484C Datasheet - Page 367

• Manufacturer Part Number: LFXP20E-4F484C
• Description: IC FPGA 19.7KLUTS 340I/O 484-BGA
• Manufacturer: Lattice

Specifications of LFXP20E-4F484C

• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant

Lattice Semiconductor
Hold Calculation
Therefore:
Isolating the board delays, we get:
Conclusion: To meet set-up and hold timings of command signals, board delay of command signals ddr_clk and
ddr_clk_n should be:
Board Design Guidelines
• The ddr_clk and ddr_clk_n pads should be placed adjacent to each other in the FPGA to get similar
• The ddr_clk and ddr_clk_n trace delays on the board should be matched.
• The DQ trace delays can be calculated using the following formula, for memory reads:
• The DQ and DQS trace lengths should be balanced and matching to get maximum set-up/hold time during
• The address and control signals for the DDR SDRAM are generated on the negative edge of the FPGA
• As shown in Figure 18-1, both FPGA internal clock and ddr_clk are generated by a single PLL. It may be
internal FPGA delays.
t
t
memory writes.
clock. The trace lengths for address and control lines are calculated using following equation:
-t
difficult to meet read data Set-up and hold timing with a single PLL. As shown in Figure 18-5, a two-PLL
clocking scheme is proposed to meet read data set-up and hold timing. Adjusting feedback delay of PLL2
can control delay of pll_mclk. Increasing delay on pll_mclk can increase the read set-up margin but it
also decreases the hold margin. To get better timing, skew between ddr_clk and pll_mclk has to be
minimized.
SKEW
DDR_CLK
Min Delay of command signals Data to DDR = t
Min Delay of Clock to DDR = t
To meet hold time at DDR memory, Data Delay - Clock Delay > 0
t
t
t
t
t
-3.709 ns < (t
CCTRL
BDCTRL
BDCTRL
BDCTRL
BDCTRL
CCTRL
+ t
(min) + t
- t
- t
- t
- t
- t
FDH
+ t
CK
BDC
BDC
BDC
BDC
FPGA_CLK
* 1/2 + t
- t
BDCTRL
> - t
> -2.147 - 3.75 + (1.138) + 0.3 + 0.75
> -3.709
> -3.709 ns
AC
BDCTRL
(min) - t
CCTRL
DDR_CLK
- t
+ t
BDC
(min) - t
PD
CK
) < 0.336 ns
- t
+ t
* 1/2 - t
DDR_CLK
SKEW
DDR_CLK
CK
* 1/2 + t
DDR_CLK
+ t
+ t
DH
(min) + t
FPGA_CLK
< (t
DDR_CLK
(min) - t
BDCTRL
BDC
18-7
CCTRL
< (t
(min) + t
+ t
BDC
- t
BDD
BDC
SKEW
(min) + t
- t
for the DDR SDRAM Controller IP Core
+ t
) < t
SKEW
+ t
SKEW
BDC
DDR_CLK
DH
- t
BDCTRL
) < (t
DH
+ t
DH
CK
> 0
+ t
+ t
* 1/2) - t
CK
CK
Board Timing Guidelines
* 1/2 - t
* 1/2
SKEW
SKEW
- t
FDS
- t
DS
- t
AC
- t
CCTRL
(max) - t
+ t
BDC
PD
-