AM28F256-150PC AMD (ADVANCED MICRO DEVICES), AM28F256-150PC Datasheet - Page 14

• Manufacturer Part Number: AM28F256-150PC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM28F256-150PC

• Lead Free Status / Rohs Status: Not Compliant

ANALYSIS OF ERASE TIMING WAVEFORM
Note: This analysis does not include the requirement
to program the entire array to 00h data prior to erasure.
Refer to the Flashrite Programming algorithm.
Erase Setup/Erase
This analysis illustrates the use of two-cycle erase
commands (section A and B). The first erase com-
mand (20h) is a Setup command and does not affect
the array data (section A). The second erase com-
mand (20h) initiates the erase operation (section B)
on the rising edge of this WE# pulse. All bytes of the
memory array are erased in parallel. No address infor-
mation is required.
The erase pulse occurs in section C.
14
Command
Bus Cycle
Function
Addresses
Section
WE
OE
Data
CE
V
V
CC
PP
#
#
#
Erase
Setup
Write
20h
A
A
Figure 2. AC Waveforms For Erase Operations
Erase
Write
20h
20h
B
B
Time-out
(10 ms)
Erase
N/A
C
20h
Am28F256
C
Time-Out
A software timing routine (10 ms duration) must be ini-
tiated on the rising edge of the WE# pulse of section B.
Note: An integrated stop timer prevents any possibil-
ity of overerasure by limiting each time-out period of
10 ms.
Erase-Verify
Upon completion of the erase software timing routine,
the microprocessor must write the Erase-verify com-
mand (A0h). This command terminates the erase oper-
ation on the rising edge of the WE# pulse (section D).
The Erase-verify command also stages the device for
data verification (section F).
After each erase operation each byte must be verified.
The byte address to be verified must be supplied with
Erase-
Verify
Write
A0h
D
A0h
D
Transition
Time-out
(6 µs)
E
N/A
E
Verification
F
Compare
Erase
Read
Data
Data
F
Out
G
Proceed per
Algorithm
Standby
Erase
N/A
11559G-7
G