AM28F256-150PC AMD (ADVANCED MICRO DEVICES), AM28F256-150PC Datasheet - Page 2

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AM28F256-150PC

Manufacturer Part Number
AM28F256-150PC
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet

Specifications of AM28F256-150PC

Lead Free Status / Rohs Status
Not Compliant

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Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as inputs to an internal state-machine which
controls the erase and programming circuitry. During
write cycles, the command register internally latches ad-
dress and data needed for the programming and erase
operations. For system design simplification, the
Am28F256 is designed to support either WE
controlled writes. During a system write cycle, ad-
dresses are latched on the falling edge of WE
whichever occurs last. Data is latched on the rising edge
of WE
BLOCK DIAGRAM
PRODUCT SELECTOR GUIDE
2
Family Part Number
Speed Options (V
Max Access Time (ns)
CE# (E#) Access (ns)
OE# (G#) Access (ns)
A0–A14
#
V CC
V SS
V PP
CE#
WE#
OE#
or CE
Low V CC
Detector
#
whichever occurs first. To simplify the fol-
CC
Command
= 5.0 V
Control
Register
State
10%)
Program/Erase
Pulse Timer
Program
#
#
Voltage
Switch
or CE
or CE
Voltage
Switch
Erase
Am28F256
#
#
-70
70
70
35
Address
Latch
lowing discussion, the WE
control pin throughout the rest of this text. All setup and
hold times are with respect to the WE
AMD’s Flash technology combines years of EPROM
and EEPROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The
Am28F256 electrically erases all bits simultaneously
using Fowler-Nordheim tunneling. The bytes are
programmed one byte at a time using the EPROM
programming mechanism of hot electron injection.
To Array
Output Enable
Chip Enable
-90
X-Decoder
Y-Decoder
90
90
35
Logic
Am28F256
-120
120
120
50
#
pin is used as the write cycle
Input/Output
Cell Matrix
DQ0–DQ7
Y-Gating
262,144
Buffers
Latch
Data
Bit
-150
150
150
55
#
signal.
11560F-1
-200
200
200
55

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