TB28F004S5-100 Intel, TB28F004S5-100 Datasheet
TB28F004S5-100
Specifications of TB28F004S5-100
Related parts for TB28F004S5-100
TB28F004S5-100 Summary of contents
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... GND, selective hardware block locking, or flexible software block locking. These alternatives give designers ultimate control of their code security needs. This family of products is manufactured on Intel industry-standard packages: the 40-lead TSOP, ideal for board-constrained applications, and the rugged 44-lead PSOP. Based on the 28F008SA architecture, the 5 Volt FlashFile memory family enables quick and easy upgrades for designs that demand state-of-the-art technology. NOTE: This document formerly known as Byte-Wide Smart 5 FlashFile™ ...
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... Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. ...
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INTRODUCTION..............................................5 8.1 New Features.............................................5 8.2 Product Overview .......................................5 8.3 Pinout and Pin Description .........................6 8.4 PRINCIPLES OF OPERATION ...................10 8.5 Data Protection ........................................10 8.6 BUS OPERATION .......................................10 8.7 Read ........................................................10 8.8 Output Disable .........................................10 8.9 Standby....................................................10 8.10 Deep Power-Down ...
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... Changed 16-Mbit commercial temperature read speed specification to equal 4- and 8-Mbit commercial temperature read speed specifications. Corrected PSOP pinout documentation error. -005 Changed document title from Byte-Wide Smart 5 FlashFile™ Memory Family 4, 8, and 16 Mbit. -006 Added information for 28F016S5 use with device code for 28F016SA ...
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... Section 8.0. 1.1 New Features The 5 Volt FlashFile memory family maintains backwards-compatibility with Intel’s 28F008SA. Key enhancements include: SmartVoltage Technology Enhanced Suspend Capabilities In-System Block Locking They share a compatible status register, software commands, and pinouts ...
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To protect programmed data, each block can be locked. This block locking mechanism uses a combination of bits, block lock-bits and a master lock-bit, to lock and unlock individual blocks. The block lock-bits gate block erase and ...
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... SUPPLY DEVICE POWER SUPPLY: Internal detection automatically configures the device CC for optimized read performance. Do not float any power pins. 5 Volt Flash With all write attempts to the flash memory are inhibited. Device CC LKO operations at invalid V results and should not be attempted. GND SUPPLY GROUND: Do not float any ground pins. ...
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... Read Array command. Block erase suspend allows system software to suspend a block erase to read data from or program data to any other block. Program suspend allows system software to suspend a program to read data from any other flash memory array location. PRELIMINARY 28F004S5, 28F008S5, 28F016S5 1FFFFF ...
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... CPU initialization may not occur because the flash IH memory may be providing status information instead of array data. Intel’s flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU ...
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Block 31 Reserved for Future Implementation 1F0002 Block 31 Lock Configuration Reserved for Future Implementation 1F0000 (Blocks 16 through 30) 0FFFFF Block 15 Reserved for Future Implementation Block 15 Lock Configuration 0F0002 Reserved for Future Implementation 0F0000 (Blocks 8 ...
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Table 2. Bus Operations Mode Notes RP# Read 1,2 Output Disable Standby Deep Power-Down Read Identifier Codes ...
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... Clear Block Lock-Bits 2 NOTES: 1. Commands other than those shown above are reserved by Intel for future device implementations and should not be used. 2. Bus operations are defined in Table Any valid address within the device Identifier Code Address: see Figure Address within the block being erased or locked. ...
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Read Array Command Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled ...
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... The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear ...
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... The only other valid commands while program is suspended are Read Status Register and Program Resume. After Program Resume command is written to the flash memory, the WSM will continue the program process. Status register bits SR.2 and SR.7 will automatically clear and RY/BY# will return to V ...
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Clear block lock-bits operation is initiated using a two-cycle command sequence. A clear block lock-bits setup is written first. Then, the device automatically outputs status register data when read (see Figure 11). The CPU can detect completion of the clear ...
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Table 6. Status Register Definition WSMS ESS ECLBS SR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS 1 = Block Erase Suspended 0 = Block Erase ...
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Start Write 20H, Block Address Write D0H, Block Address Read Status Register Suspend Block Erase Loop No 0 Suspend SR.7 = Block Erase Yes 1 Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register ...
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Start Write 40H, Address Write Byte Data and Address Read Status Register Suspend Program Loop No 0 Suspend SR.7 = Program 1 Full Status Check if Desired Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data ...
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Start Write B0H Read Status Register 0 SR SR.6 = Block Erase Completed 1 Read Program Read or Program ? Program Read Array No Loop Data Done? Yes Write D0H Write FFH Block Erase Resumed Read Array ...
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Start Write B0H Read Status Register 0 SR Program Completed SR Write FFH Read Array Data No Done Reading Yes Write D0H Write FFH Program Resumed Read Array Data Figure 9. Program ...
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Start Write 60H, Block/Device Address Write 01H/F1H, Block/Device Address Read Status Register 0 SR Full Status Check if Desired Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above Range Error ...
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Start Write 60H Write D0H Read Status Register 0 SR Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above Range Error ...
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... DESIGN CONSIDERATIONS 5.1 Three-Line Output Control Intel provides three control inputs to accommodate multiple memory connections: CE#, OE#, and RP#. Three-line control provides for: a. Lowest possible memory power dissipation. b. Data bus contention avoidance. To use these control inputs efficiently, an address decoder should enable CE# while OE# should be connected to all memory devices and the system’ ...
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... Sampled, not 100% tested. 26 NOTICE: This datasheet contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design. * WARNING: Stressing the device beyond the "Absolute Maximum Ratings" ...
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DC Characteristics— Commercial Temperature Sym Parameter Notes I Input Load Current Output Leakage Current Standby Current 1,3,6 CCS Deep Power-Down 1 CCD CC Current I V Read Current 1,5,6 ...
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DC Characteristics— Commercial Temperature Sym Parameter Notes V Input Low Voltage Input High Voltage Output Low Voltage 3 Output High Voltage 3,7 OH1 (TTL) V Output High Voltage ...
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INPUT 1.5 0.0 AC test inputs are driven at 3.0 V for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at 1.5 V. Input rise and fall times (10% to ...
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V IH RY/BY# ( RP# ( Figure 15. AC Waveform for Reset Operation Table 7. Reset Specifications # Sym P1 t RP# Pulse Low Time PLPH (If RP# is tied ...
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AC Characteristics— Read-Only Operations °C to +70 °C A Versions (4) # Sym Parameter R1 t Read Cycle Time 4, 8 Mbit AVAV 16 Mbit R2 t Address to Output 4, 8 Mbit AVQV 16 Mbit ...
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Standby V IH ADDRESSES ( CE# ( OE# ( WE# ( DATA (D/Q) High Z (DQ0-DQ7 ...
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AC Characteristics— Write Operations °C to +70 °C A Versions (4) # Sym RP# High Recovery to WE# (CE#) Going Low PHWL PHEL CE# (WE#) Setup to WE# ...
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ADDRESSES [ CE# (WE#) [E(W OE# [ WE# (CE#) [W(E ...
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Block Erase, Program, and Lock-Bit Configuration Performance Commercial Temperature ± 0 ± 0. °C to +70 ° Sym Parameter W16 t Program Time WHRH1 t ...
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... Current NOTE: 1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds). Contact Intel’s Application Support Hotline or your local sales office for information about typical specifications. 6.10 AC Characteristics—Read-Only Operations T = –40 °C to +85 °C ...
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... Mbit 8 Mbit Commercial Temperature E28F004S5-85 E28F008S5-85 E28F004S5-120 E28F008S5-120 PA28F004S5-85 PA28F008S5-85 PA28F004S5-120 PA28F008S5-120 TE28F004S5-100 TE28F008S5-100 TB28F004S5-100 TB28F008S5-100 NOTE: 1. Valid access time for 16-Mbit 5 Volt FlashFile memory. 2. 28F016S5 with device code for 28F016SA. PRELIMINARY 28F004S5, 28F008S5, 28F016S5 ® Flash products 5 Access Speed (ns) ...
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... Models Sales Office NOTES: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel’s World Wide Web home page at http://www.intel.com for technical documentation and tools. ...