TE28F004B5B80 Intel, TE28F004B5B80 Datasheet - Page 17

• Manufacturer Part Number: TE28F004B5B80
• Manufacturer: Intel

Specifications of TE28F004B5B80

• Cell Type: NOR
• Density: 4Mb
• Access Time (max): 80ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 19b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 512K
• Supply Current: 70mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

these bits, several operations (such as cumulatively
erasing multiple blocks or programming several
bytes in sequence) may be performed before
polling the status register to determine if an error
occurred during the series.
Issue the Clear Status Register command (50H) to
clear the status register. It functions independently
of the applied V
V
erase suspend modes. Resetting the part with RP#
also clears the status register.
3.2.4
Word or byte program operations are executed by a
two-cycle command sequence. Program Set-Up
(40H) is issued, followed by a second write that
specifies the address and data (latched on the
rising edge of WE# or CE#, whichever comes first).
The WSM then takes over, controlling the program
and program verify algorithms internally. While the
WSM is working, the device automatically enters
read status register mode and remains there after
the word/byte program is complete. (see Figure 8).
The completion of the program event is indicated on
status register bit SR.7.
When a word/byte program is complete, check
status register bit SR.4 for an error flag (“1”). The
cause of a failure may be found on SR.3, which
indicates “1” if V
voltage range (V
should be cleared before the next operation. The
internal WSM verify only detects errors for “1”s that
do not successfully write to “0”s.
Since the device remains in status register read
mode after programming is completed, a command
must be issued to switch to another mode before
beginning a different operation.
3.2.5
A block erase changes all block data to 1’s
(FFFFH) and is initiated by a two-cycle command.
An Erase Set-Up command (20H) is issued first,
followed by an Erase Confirm command (D0H)
along with an address within the target block. The
address will be latched at the rising edge of WE# or
CE#, whichever comes first.
Internally, the WSM will program all bits in the block
to “0,” verify all bits are adequately programmed to
HH
PRELIMINARY
. This command is not functional during block
WORD/BYTE PROGRAM
BLOCK ERASE
PP
PPH1
PP
voltage and RP# can be V
or V
was out of program/erase
PPH2
). The status register
IH
or
“0,” erase all bits to “1,” and verify that all bits in the
block are sufficiently erased. After block erase
command
automatically enters read status register mode and
outputs status register data when read (see
Figure 9). The completion of the erase event is
indicated on status register bit SR.7.
When an erase is complete, check status register
bit SR.5 for an error flag (“1”). The cause of a failure
may be found on SR.3, which indicates “1” if V
was out of program/erase voltage range (V
V
issued but not followed by an Erase Confirm (D0H)
command, then both the program status (SR.4) and
the erase status (SR.5) will be set to “1.”
The status register should be cleared before the
next operation. Since the device remains in status
register read mode after erasing is completed, a
command must be issued to switch to another
mode before beginning a different operation.
3.2.5.1
The Erase Suspend command (B0H) interrupts an
erase operation in order to read data in another
block of memory. While the erase is in progress,
issuing the Erase Suspend command requests that
the WSM suspend the erase algorithm after a
certain latency period. After issuing the Erase
Suspend command, write the Read Status Register
command, then check bit SR.7 and SR.6 to ensure
the device is in the erase suspend mode (both will
be set to “1”). This check is necessary because the
WSM may have completed the erase operation
before the Erase Suspend command was issued. If
this occurs, the Erase Suspend command would
switch the device into read array mode. See
Appendix A for a comprehensive chart showing the
state transitions.
When erase has been suspended, a Read Array
command (FFH) can be written to read from blocks
other than that which is suspended. The only other
valid commands at this time are Erase Resume
(D0H) or Read Status Register.
During erase suspend mode, the chip can go into a
pseudo-standby mode by taking CE# to V
reduces active current draw. V
V
erase) while erase is suspended. RP# must also
remain at V
block erase).
PPH2
PPH1
). If an Erase Set-Up (20H) command is
or V
28F200B5, 28F004/400B5, 28F800B5
PPH2
IH
sequence
Erase Suspend/Resume
or V
(the same V
HH
(the same RP# level used for
is
PP
issued,
level used for block
PP
must remain at
the
IH
PPH1
, which
device
17
PP
or