CY7C68001-56PVC Cypress Semiconductor Corp, CY7C68001-56PVC Datasheet - Page 8

• Manufacturer Part Number: CY7C68001-56PVC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C68001-56PVC

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: SSOP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

6. Enumeration
The SX2 has two modes of enumeration. The first mode is
automatic through EEPROM boot load, as described in
Methods
descriptor or VID, PID, and DID as described in the following
section.
6.1 Standard Enumeration
The SX2 has 500 bytes of descriptor RAM into which the external
master may write its descriptor. The descriptor RAM is accessed
through register 0x30. To load a descriptor, the external master
does the following:
■
■
■
After the entire descriptor has been transferred, the SX2 floats
the pull up resistor connected to D+, and parse through the
descriptor to locate the individual descriptors. After the SX2 has
parsed the entire descriptor, the SX2 connects the pull up
resistor and enumerate automatically. When enumeration is
complete, the SX2 notifies the external master with an ENUMOK
interrupt.
The format and order of the descriptor should be as follows (see
Default Descriptor
■
■
■
■
■
The SX2 can be set to run in full speed only mode. To force full
speed only enumeration write a 0x02 to the unindexed register
CT1 at address 0xE6FB before downloading the descriptors.
This disables the chirp mechanism forcing the SX2 to come up
in full speed only mode after the descriptors are loaded. The CT1
register can be accessed using the unindexed register
mechanism. Examples of writing to unindexed registers are
shown in
of a command write with the target register followed by the write
of the upper nibble of the value followed by the write of the lower
nibble of the value.
Document #: 38-08013 Rev. *K
Note
6. These and all other data bytes must conform to the command protocol.
Initiate a Write Request to register 0x30.
Write two bytes (four command data transfers) that define the
length of the entire descriptor about to be transferred. The LSB
is written first, followed by the MSB.
Write the descriptor, one byte at a time until complete.
the register address is only written once.
Device.
Device qualifier.
High speed configuration, high speed interface, high speed
endpoints.
Full speed configuration, full speed interface, full speed
endpoints.
String.
on page 2. The second method is a manual load of the
Resetting Data Toggle
on page 37 for an example):
on page 9. Each write consists
[6]
[6]
Note:
Boot
6.2 Default Enumeration
The external master may simply load a VID, PID, and DID and
use the default descriptor built into the SX2. To use the default
descriptor, the descriptor length described in the previous
section must equal 6. After the external master has written the
length, the VID, PID, and DID must be written LSB, then MSB.
For example, if the VID, PID, and DID are 0x04B4, 0x1002, and
0x0001 respectively, then the external master does the following:
■
■
■
The default descriptor is listed in
The default descriptor can be used as a starting point for a
custom descriptor.
7. Endpoint 0
The SX2 automatically responds to USB chapter 9 requests
without any external master intervention. If the SX2 receives a
request to which it cannot respond automatically, the SX2
notifies the external master. The external master then has the
choice of responding to the request or stalling.
After the SX2 receives a setup packet to which it cannot respond
automatically, the SX2 asserts a SETUP interrupt. After the
external master reads the Interrupt Status Byte to determine that
the interrupt source was the SETUP interrupt, it can initiate a
read request to the SETUP register, 0x32. When the SX2 sees
a read request for the SETUP register, it presents the first byte
of setup data to the external master. Each additional read
request presents the next byte of setup data, until all eight bytes
have been read.
The external master can stall this request at this or any other
time. To stall a request, the external master initiates a write
request for the SETUP register, 0x32, and writes any non-zero
value to the register.
If this setup request has a data phase, the SX2 then interrupts
the external master with an EP0BUF interrupt when the buffer
becomes available. The SX2 determines the direction of the
setup request and interrupts when either:
■
■
For an IN setup transaction, the external master can write up to
64 bytes at a time for the data phase. The steps to write a packet
are as follows:
1. Wait for an EP0BUF interrupt, indicating that the buffer is
2. Initiate a write request for register 0x31.
3. Write one data byte.
4. Repeat steps 2 and 3 until either all the data or 64 bytes have
5. Write the number of bytes in this packet to the byte count
Initiates a Write Request to register 0x30.
Writes two bytes (four command data transfers) that define the
length of the entire descriptor about to be transferred. In this
case, the length is always six.
Writes the VID, PID, and DID bytes: 0xB4, 0x04, 0x02, 0x10,
0x01, 0x00 (in nibble format per the command protocol).
IN: the Endpoint 0 buffer becomes available to write to, or
OUT: the Endpoint 0 buffer receives a packet from the USB
host.
available.
been written, whichever is less.
register, 0x33.
Default Descriptor
CY7C68001
Page 8 of 45
on page 37.
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