RC28F320C3TD90 Micron Technology Inc, RC28F320C3TD90 Datasheet - Page 40

• Manufacturer Part Number: RC28F320C3TD90
• Manufacturer: Micron Technology Inc

Specifications of RC28F320C3TD90

• Lead Free Status / Rohs Status: Not Compliant

9.1.5
Datasheet
40
impedance state independent of OE#. If deselected during a Program or Erase
operation, the device continues to consume active power until the Program or Erase
operation is complete.
Reset
From read mode, RP# at V
in a high-impedance state, and turns off all internal circuits. After return from reset, a
time t
t
wake-up interval, normal operation is restored. The CUI resets to read-array mode, the
Status Register is set to 0x80, and all blocks are locked. See
Operations Waveforms” on page
If RP# is taken low for time t
will be aborted; the memory contents at the aborted location (for a program) or block
(for an erase) are no longer valid, since the data may be partially erased or written.
The abort process goes through the following sequence:
In both cases, after returning from an aborted operation, the relevant time t
t
in the previous paragraph. However, in this case, these delays are referenced to the
end of t
As with any automated device, it is important to assert RP# during a system reset.
When the system comes out of reset, the processor reads from the flash memory.
Automated flash memories provide status information when read during Program or
Block-Erase operations. If a CPU reset occurs with no flash memory reset, proper CPU
initialization may not occur because the flash memory may be providing status
information instead of array data. Numonyx™ flash memories allow proper CPU
initialization following a system reset through the use of the RP# input. In this
application, RP# is controlled by the same RESET# signal that resets the system CPU.
PHEL
PHWL
1. When RP# goes low, the device shuts down the operation in progress, a process
2. After time t
which takes time t
during t
“Reset Operations Waveforms” on page
) is required after return from reset before a write cycle can be initiated. After this
/t
PHQV
PHEL
PLRH
is required until the initial read-access outputs are valid. A delay (t
must be observed before a Read or Write operation is initiated, as discussed
PLRH
rather than when RP# goes high.
PLRH
) or enter reset mode (if RP# is deasserted after t
, the part will either reset to read-array mode (if RP# is asserted
PLRH
IL
to complete.
for time t
PLPH
38.
during a Program or Erase operation, the operation
PLPH
deselects the memory, places output drivers
38.
Figure 13, “Reset
PLRH
). See
Figure 13,
PHQV
C3 Discrete
PHWL
March 2008
290645-24
or
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