LMX2326TM National Semiconductor, LMX2326TM Datasheet - Page 12

• Manufacturer Part Number: LMX2326TM
• Manufacturer: National Semiconductor
• Type: PLL Frequency Synthesizerr

Specifications of LMX2326TM

• Number Of Elements: 1
• Supply Current: 7mA
• Pll Input Freq (min): 100MHz
• Pll Input Freq (max): 2.8GHz
• Operating Supply Voltage (typ): 3V
• Operating Temp Range: -40C to 85C
• Package Type: TSSOP
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Pin Count: 16
• Lead Free Status / Rohs Status: Not Compliant

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1.0 Functional Description
Note 7: When the GO bit N[19] is set to one, the part is forced into the high gain mode. When the timeout counter is activated, termination of the counter cycle resets
the GO bit to 0. If the timeout counter is not activated, N[19] must be reprogrammed to zero in order to remove the high gain state. See below for descriptions of
each individual FastLock mode.
There are two techniques of switching in and out of FastLock. To program the device into any of the FastLock modes, the GO bit
N[19] must be set to one to begin FastLock operation. In the first approach, the timeout counter can be used (FastLock 2 and 4)
to stay in FastLock mode for a programmable number of phase detector reference cycles (up to 63) and then reset the GO bit
automatically. In the second approach (FastLock 1 and 3) without the timeout counter, the PLL will remain in FastLock mode until
the user resets the GO bit via the MICROWIRE serial bus. Once the GO bit is set to zero by the timeout counter or by
MICROWIRE, the PLL will then return to normal operation. This transition does not effect the charge on the loop filter capacitors
and is enacted synchronous with the charge pump output. This creates a nearly seamless transition between FastLock and
standard mode.
FastLock Mode 1 In this mode, the output level of the FL
FastLock Mode 2 Identical to mode 1, except the switching of the device out of FastLock is controlled by the Timeout counter.
FastLock Mode 3 This mode is similar to mode 1 in that the output level of the FL
FastLock Mode 4 Identical to mode 3, except the switching of the device out of FastLock is controlled by the Timeout counter.
*Normal Operation FastLock Normal Operation is defined as the device being in low current mode and standard divider values.
FastLock Mode #1
FastLock Mode #2
FastLock Mode #3
FastLock Mode #4
FastLock Status
device remains in this state until a command is received, resetting the N[19] bit to zero. Programming N[19]
to zero will return the device to normal operation*., i.e., ICP
The device will remain in FastLock until the timeout counter has counted down the appropriate number of
phase detector cycles, at which time the PLL returns to normal operation*.
state. Additionally, the R and N divide ratios are reduced by one fourth during the transient, resulting in a 16x
improved gain. As in mode 1, the device remains in this state until a MICROWIRE command is received,
resetting the N[19] bit to zero and returning the device to normal operation*.
The device will remain in FastLock until the timeout counter has counted down the appropriate number of
phase detector cycles, at which time the PLL returns to normal operation*.
F[8]
1
1
1
1
F[9]
0
0
1
1
(Continued)
TABLE 5. FastLock Decoding
F[10]
0
1
0
1
o
is programmed in a low state while the ICP
12
1 (Note 7)
1 (Note 7)
(Note 7)
N[19]
1
1
o
= 1x and FL
No Timeout Counter - 1X Divider
Timeout Counter - 1X Divider
No Timeout Counter - 1/4X Divider
Timeout Counter - 1/4X Divider
o
is low and the ICP
o
FastLock State
returned to TRI-STATE.
o
o
is in the 4x state. The
is switched to the 4x
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