21281EB Intel, 21281EB Datasheet - Page 12

• Manufacturer Part Number: 21281EB
• Manufacturer: Intel

Specifications of 21281EB

• Family Name: SA-110
• Frequency (max): 233MHz
• Supply Voltage 1 (typ): 2V
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

Errata
Errata
1.
Problem:
Implication:
8
Potential Data Abort Occurs in Some Demand-Paged Memory-Management
Schemes
There is an anomaly in the SA-110 device that may occur during a DATA_ABORT in environ-
ments that use demand-paged memory-management schemes. This problem has been seen only in
demand-page memory-management operating systems when a memory access crosses a page
boundary from a mapped page to an unmapped page during the sequence of data fetches.
Designs using operating systems with demand-page memory management schemes are susceptible
to this problem. Designs using operating systems without demand-page memory management
schemes are not susceptible to this problem.
Check with your RTOS vendor to verify the method of memory-management scheme used to
determine if your design is susceptible to this problem.
The Rn register may be incorrectly updated when a DATA_ABORT occurs during a load multiple
registers, increment before (LDMIB) instruction. There is no known way to reliably replay the
instruction after the data abort condition is corrected.
Problem conditions are:
If the instruction takes a DATA_ABORT after the first load completes successfully, the SA-110
incorrectly restores the base address register to base + 4. If the abort occurs immediately, the base
address register is left at the correct value.
If a DATA_ABORT returns Rn with a value of Page_Boundary_Address (PBA) minus 4, it is unclear
if the address is correct or if the correct address is PBA-8 with at least one register updated.
In actual operation, no code streams or data fetches are expected to DATA_ABORT at runtime
(that is, any active process is fully mapped at runtime).
1. The register list to be updated includes the base address register Rn.
2. The LDMIB causes a data abort.
3. At least one register is loaded successfully prior to the abort.
C-EXECUTIVE*
Helios*
Kadak
Precise/MQX*
RTXC
LDMIB Rn, {register list including Rn}
Rn = Rn + 4 (original value +4)
If the abort occurs with no register loaded, Rn = Rn (the correct value).
Epoch32
Java* OS
Newton OS
pSOS
Wind River
SA-110
Specification Update