JS28F640J3C115 Intel, JS28F640J3C115 Datasheet - Page 5

• Manufacturer Part Number: JS28F640J3C115
• Manufacturer: Intel

Specifications of JS28F640J3C115

• Cell Type: NOR
• Density: 64Mb
• Access Time (max): 115ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 23/22Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 8M/4M
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Compliant

Revision History
Datasheet
Revision
07/07/99
08/03/99
09/07/99
12/16/99
03/16/00
06/26/00
04/13/01
Date of
2/15/01
Version
-001
-002
-003
-004
-005
-006
-007
-008
Original Version
A
Changed Minimum Block Erase time,I
currents. Modified RP# on AC Waveform for Write Operations
Changed Block Erase time and t
Removed all references to 5 V I/O operation
Corrected Ordering Information, Valid Combinations entries
Changed Min program time to 211 µs
Added DU to Lead Descriptions table
Changed Chip Scale Package to Ball Grid Array Package
Changed default read mode to page mode
Removed erase queuing from Figure 10, Block Erase Flowchart
Added Program Max time
Added Erase Max time
Added Max page mode read current
Moved tables to correspond with sections
Fixed typographical errors in ordering information and DC parameter table
Removed V
Added recommended resister value for STS pin
Change operation temperature range
Removed note that rp# could go to 14 V
Removed V
Updated I
Added Max lock-bit program and lock times
Added note on max measurements
Updated cover sheet statement of 700 million units to one billion
Corrected Table 10 to show correct maximum program times
Corrected error in Max block program time in section 6.7
Corrected typical erase time in section 6.7
Updated cover page to reflect 100K minimum erase cycles
Updated cover page to reflect 110 ns 32M read speed
Removed Set Read Configuration command from Table 4
Updated Table 8 to reflect reserved bits are 1-7; not 2-7
Updated Table 16 bit 2 definition from R to PSS
Changed V
Characteristics
Updated 32Mbit Read Parameters R1, R2 and R3 to reflect 110ns, Section 6.5,
AC Characteristics–Read-Only Operations
Updated write parameter W13 (t
Characteristics–Write Operations
Updated Max. Program Suspend Latency W16 (t
Section 6.7, Block Erase, Program, and Lock-Bit Configuration Performance
(1,2,3)
Revised Section 7.0, Ordering Information
0
–A
2
indicated on block diagram
CCR
PENLK
CCQ1
OL
Typ values
of 0.45 V; Removed V
setting and changed V
Max voltage from 0.8 V to 2.0 V, Section 6.4, DC
WHRL
AVWH
Description
OH
) from 90 ns to 500 ns, Section 6.6, AC
OL
CCQ2/3
, I
of 2.4 V
OH
(1,2)
, Page Mode and Byte Mode
to V
WHRH1
CCQ1/2
) from 30 to 75 µs,
Contents
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