DSPB56364FU100 Freescale Semiconductor, DSPB56364FU100 Datasheet - Page 11

• Manufacturer Part Number: DSPB56364FU100
• Manufacturer: Freescale Semiconductor

Specifications of DSPB56364FU100

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 9KB
• Program Memory Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.14V
• Operating Supply Voltage (max): 3.46V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• Lead Free Status / Rohs Status: Not Compliant

2.7
The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I
Freescale Semiconductor
Signal
Name
MISO
MOSI
SCK
SCL
SDA
open-drain
Serial Host Interface
Input or
Input or
Input or
Input or
Input or
Signal
output
output
output
output
output
Type
State During
Tri-stated
Tri-stated
Tri-stated
Tri-stated
Tri-stated
Reset
Table 2-9 Serial Host Interface Signals
SPI Serial Clock—The SCK signal is an output when the SPI is configured as a master
and a Schmitt-trigger input when the SPI is configured as a slave. When the SPI is
configured as a master, the SCK signal is derived from the internal SHI clock generator.
When the SPI is configured as a slave, the SCK signal is an input, and the clock signal
from the external master synchronizes the data transfer. The SCK signal is ignored by
the SPI if it is defined as a slave and the slave select (SS) signal is not asserted. In both
the master and slave SPI devices, data is shifted on one edge of the SCK signal and is
sampled on the opposite edge where data is stable. Edge polarity is determined by the
SPI transfer protocol.
I
is a Schmitt-trigger input when configured as a slave and an open-drain output when
configured as a master. SCL should be connected to V
This signal is tri-stated during hardware, software, and individual reset. Thus, there is
no need for an external pull-up in this state.
This input is 5 V tolerant.
SPI Master-In-Slave-Out—When the SPI is configured as a master, MISO is the
master data input line. The MISO signal is used in conjunction with the MOSI signal for
transmitting and receiving serial data. This signal is a Schmitt-trigger input when
configured for the SPI Master mode, an output when configured for the SPI Slave
mode, and tri-stated if configured for the SPI Slave mode when SS is deasserted. An
external pull-up resistor is not required for SPI operation.
I
receiving and an open-drain output when transmitting. SDA should be connected to
V
SDA must be stable during the high period of SCL. The data in SDA is only allowed to
change when SCL is low. When the bus is free, SDA is high. The SDA line is only
allowed to change during the time SCL is high in the case of start and stop events. A
high-to-low transition of the SDA line while SCL is high is a unique situation, and is
defined as the start event. A low-to-high transition of SDA while SCL is high is a unique
situation defined as the stop event.
This signal is tri-stated during hardware, software, and individual reset. Thus, there is
no need for an external pull-up in this state.
This input is 5 V tolerant.
SPI Master-Out-Slave-In—When the SPI is configured as a master, MOSI is the
master data output line. The MOSI signal is used in conjunction with the MISO signal
for transmitting and receiving serial data. MOSI is the slave data input line when the
SPI is configured as a slave. This signal is a Schmitt-trigger input when configured for
the SPI Slave mode.
2
2
CC
C Serial Clock—SCL carries the clock for I
C Data and Acknowledge—In I
DSP56364 Technical Data, Rev. 4.1
through a pull-up resistor. SDA carries the data for I
Signal Description
2
C mode, SDA is a Schmitt-trigger input when
2
C bus transactions in the I
CC
2
C transactions. The data in
through a pull-up resistor.
Serial Host Interface
2
C mode. SCL
2
C mode.
2-7