ELANSC400-66AC AMD (ADVANCED MICRO DEVICES), ELANSC400-66AC Datasheet - Page 15

• Manufacturer Part Number: ELANSC400-66AC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ELANSC400-66AC

• Cpu Family: Elan
• Device Core Size: 16/32Bit
• Frequency (max): 66MHz
• Interface Type: ISA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 95C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 292
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

ROM/Flash Memory Interface
The integrated ROM/Flash memory interface supports
the following features:
Each ROM space can accommodate up to 64 Mbyte of
ROM. The three ROM spaces can be individually write-
protected. This is useful for protecting code residing in
Flash memory devices.
Two of the three ROM/Flash memory chip selects can
be remapped to a PC Card socket via pinstrap or soft-
ware control. This feature supports reprogramming of
soldered-down Flash memory boot devices and also
simplifies testing of BIOS/XIP OS code.
Three ROM access modes are supported: Normal
mode, Fast mode, and Burst mode. A different set of
timings is used in each mode. In Normal ROM access
mode, the bus cycles follow ISA-like timings. In Fast
ROM access mode, the bus cycle timing occurs at the
CPU clock rate with controls for wait-state insertion.
Burst ROM access timing is used when the ROM/Flash
memory interface is fulfilling an internal CPU burst re-
quest to support a cache line refill.
Wait states are supported for all ROM and Flash mem-
ory accesses, including Burst mode. Burst-mode
(page-mode) ROM reads are supported for either a
16- or 32-bit ROM interface running in Fast mode.
DRAM Controller
The integrated DRAM controller provides the signals and
associated timing necessary to support an external
DRAM array with minimal software programming and
overhead. Internal programmable registers are provided
to select the DRAM type and operating mode, as well as
refresh options. A wide variety of commodity DRAMs are
supported, and substantial flexibility is built into the DRAM
controller to optimize performance of the CPU and (on the
ÉlanSC400 microcontroller) the internal graphics control-
ler, which uses system DRAM for its buffers.
The DRAM controller supports the following features:
8-, 16-, and 32-bit ROM/Flash memory interfaces
Three ROM/Flash memory chip selects
Burst-mode ROMs
ROM accesses at both ISA and CPU speeds
(normal and fast-speed modes)
Dedicated ROM Read and ROM Write signals for
better performance
3.3-V, 70-ns DRAMs
Up to four banks
16-bit or 32-bit banks
Up to 64 Mbyte of total memory
Self-refresh DRAMs
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
Integrated Standard PC/AT Peripherals
The ÉlanSC400 and ÉlanSC410 microcontrollers in-
clude all the standard peripheral controllers that make
up a PC/AT system.
Dual DMA Controllers
Dual, cascaded, 8237A-compatible DMA controllers
provide seven user-definable DMA channels. Of the
seven internal channels, four are 8-bit channels and
three are 16-bit channels. Channel 4 is used for the cas-
cade function.
Any two of the seven channels can be mapped simul-
taneously to external DMA request/acknowledge lines.
The DMA controller on the ÉlanSC400 and ÉlanSC410
microcontrollers is software compatible with the PC/AT
cascaded 8237 controller pair. Its features include:
Dual Interrupt Controllers
Dual, cascaded, 8259-compatible programmable
interrupt controllers support 15 user-definable interrupt
levels. Eight external interrupt requests can be mapped
to any of the 15 internal IRQ inputs.
The interrupt controller block includes these features:
Fast page and Extended Data Out (EDO) DRAMs
Two-way interleaved operation among identically
populated banks using fast-page mode devices
Mixed depth and width of DRAM banks in non-inter-
leaved mode
Symmetrical and asymmetrical DRAM support
Single, block, and demand transfer modes
Enable/disable channel controller
Address increment or decrement
Software priority
64-Mbyte system address space for increased
performance
Dynamic clock-enable design for reducing clocked
elements during DMA inactivity
Programmable clock frequency for performance
Software-compatibility with PC/AT interrupt controllers
15-level priority controller
Programmable interrupt modes
Individual interrupt request mask capability
Accepts requests from peripherals
Resolves priority on pending interrupts and
interrupts in service
Issues interrupt request to processor
Provides interrupt vectors for interrupt service routines
Tied into the PMU for power management
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