DT28F160F3T95 Intel, DT28F160F3T95 Datasheet
DT28F160F3T95
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DT28F160F3T95 Summary of contents
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... Volt Fast Boot Block Flash memory offers the highest performance synchronous burst reads— making it an ideal memory solution for burst CPUs. The Intel 3 Volt Fast Boot Block Flash memory also supports asynchronous page mode operation for non-clocked memory subsystems. Combining high read ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel’s website at http://www.intel.com. ...
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Contents 1.0 Introduction .................................................................................................................. 1 1.1 Product Overview .................................................................................................. 1 2.0 Product Description 2.1 Pinouts .................................................................................................................. 2 2.2 Pin Description ...................................................................................................... 2 2.3 Memory Blocking Organization ............................................................................. 5 2.3.1 Parameter Blocks ..................................................................................... 5 2.3.2 Main Blocks .............................................................................................. 5 3.0 Principles ...
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Standby Power.................................................................................................... 25 7.4 Power-Up/Down Operation ................................................................................. 26 7.4.1 RST# Connection................................................................................... 26 7.4.2 VCC, VPP and RST# Transitions........................................................... 26 7.5 Power Supply Decoupling ................................................................................... 26 7.5.1 VPP Trace on Printed Circuit Boards ..................................................... 27 8.0 Electrical Specifications 8.1 ...
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Revision History Date of Version Revision 10/01/99 -001 08/03/00 -002 03/26/01 -003 PRELIMINARY Description Original version Removed all references and 1.65 V I/O capability. Removed -125 ns device and added 80ns device. Changed t time from 19 ...
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... Introduction This datasheet contains 8-Mbit 3 Volt Intel 1.0 provides a flash memory overview. Sections 2.0 through 8.0 describe the memory functionality and electrical specifications for automotive temperature product offerings. 1.1 Product Overview The 3 Volt Fast Boot Block Flash memory provides density upgrades with pinout compatibility for 8-Mbit densities ...
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... This section describes the pinout and block architecture of the device family. 2.1 Pinouts Intel 3 Volt Fast Boot Block Flash memory provides upgrade paths in each package pinout up to the 8-Mbit density. The family is available in Easy BGA and 56-lead SSOP packages. Ballout for the Easy BGA is illustrated in ...
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... All locations are populated with solder balls. 2. Shaded connections on the Top View indicate possible future upgrade address connections. 3. Reference the Preliminary Mechanical Specification for Easy BGA Package at the Intel® Flash Packaging Data website, http://developer.intel.com/design/flash/packdata/index.htm, for detailed package specifications. ...
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... DQ OUTPUT 15 when the chip is deselected or outputs are disabled. Data is internally latched during a write cycle. CLOCK: Synchronizes the flash memory to the system operating frequency during synchronous burst mode read operations. When configured for synchronous burst-mode reads, the address is latched on CLK INPUT the first rising (or falling, depending upon the read configuration register setting) CLK edge when ADV# is active or upon a rising ADV# edge, whichever occurs first ...
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... Memory Blocking Organization The 3 Volt Fast Boot Block Flash memory family is an asymmetrically-blocked architecture that enables system integration of code and data within a single flash device. For the address locations of each block, see the memory maps in Map” on page 6. 8-Mbit Top Boot and Bottom Boot Blocking. ...
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Figure 3. 8- Mbit Top Boot and Bottom Boot Memory Map 8-Mbit 4-KWord Parameter Block 22 4-KWord Parameter Block 21 4-KWord Parameter Block 20 4-KWord Parameter Block 19 4-KWord Parameter Block 18 4-KWord Parameter Block 17 4-KWord Parameter Block ...
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... It allows for CMOS-level control inputs, fixed power supplies, and minimal processor overhead with RAM-like interface timings. 3.1 Bus Operations The local CPU reads and writes flash memory in-system. All flash memory read and write cycles conform to standard microprocessor bus cycles. 3.1.1 Read The flash memory has three read modes available: read array, identifier codes, and status register ...
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Standby Deselecting the device by bringing CE logic-high level (V mode, which substantially reduces device power consumption. In standby, outputs are placed in a high-impedance state independent of OE#. If deselected during program or erase operation, ...
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... Block Erase and Program Suspend Block Erase and Program Resume Set Read Configuration NOTES: 1. Commands other than those shown above are reserved by Intel for future device implementations and should not be used. 2. Bus operations are defined Any valid address within the device. ...
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SRD = Data read from status register. See of the status register bits Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first). ID ...
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CLK edge when ADV# is low during synchronous burst mode or the falling edge of OE# or CE#, whichever occurs first. The Read Status Register command functions independently of the V voltage. 4.4 Clear Status Register Command Status register bits ...
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Table 5. Status Register Definition WSMS ESS SR.7 = WRITE STATE MACHINE STATUS (WSMS Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS (ESS Block Erase Suspended 0 = Block Erase ...
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... Program Suspend/Resume Command The Program Suspend command allows program interruption to read data in other flash memory locations. Once the program process starts, writing the Program Suspend command requests that the WSM suspend the program operation after a certain latency period. The device continues to output status register data when read after issuing the Program Suspend command ...
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... These bits are reserved for future use. Set these bits to “0.” Undocumented combinations of bits RCR.10–9 are reserved by Intel Corporation for future implementations and should not be used. In the asynchronous page mode, the burst length always equals four words. Undocumented combinations of bits RCR.2– ...
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... The frequency configuration codes in Table 7 are derived from equations (1), (2) and (3) with assumed values for the t calculation to obtain the frequency configuration code: Flash performance can be determined by the following equations: {1/Frequency (MHz)} = CLK Period (ns) n(CLK Period) t n-2 = Frequency Configuration Code (FCC) ...
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Figure 4. Data Output with FCC Setting at Code 3 CLK (C) CE# ADV 15-0 NOTE: 1. Figure 4 shows the data output available and valid after 4 latencies from ADV# going low in the 1st clock ...
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Table 7. Frequency Configuration Settings Frequency Configuration Code NOTE: Table derived by using formulas (1), (2) and (3) in assumed and 4 ns respectively; value of t 4.9.3 Data Output ...
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... Burst Sequence – (RCR.7) The burst sequence specifies the order in which data is addressed in synchronous burst mode. This order is programmable as either linear or Intel burst order. The continuous burst length only supports linear burst order. The order chosen will depend on the CPU characteristic. See for more details ...
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... Continuous Burst Length When operating in the continuous burst mode, the flash memory may incur an output delay when the burst sequence crosses the first 16-word boundary. The starting address dictates whether or not a delay will occur. If the starting address is aligned to a four-word boundary, the delay will not be seen. If the starting address is the end of a four-word boundary, the output delay will be equal to the frequency configuration setting ...
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Figure 7. Automated Block Erase Flowchart Start Write 20H, Block Address Write D0H, Block Address Read Status Register SR Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) ...
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Figure 8. Automated Program Flowchart Start Write 40H, Address Write Data and Address Read Status Register SR Full Status Check if Desired Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR SR.1 ...
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Figure 9. Block Erase Suspend/Resume Flowchart Start Write B0H Read Status Register SR.7 = SR.6 = Read Read or Byte Write? Read Array Data Done Write D0H Block Erase Resumed 22 Bus Operation Standby Standby Block ...
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Figure 10. Program Suspend/Resume Flowchart Start Write B0H Read Status Register SR SR Write FFH Read Array Data Done Reading Yes Write D0H Program Resumed PRELIMINARY Bus Operation Write Read Standby 0 Standby Write 0 Program ...
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... Data Protection The 3 Volt Fast Boot Block Flash memory architecture features two hardware-lockable parameter blocks, so critical code can be kept secure while six other parameter blocks can be programmed or erased as necessary to facilitate EEPROM emulation. 5 PPLK The V programming voltage can be held low for complete write protection of all blocks in the PP flash device ...
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... V Voltages PP Intel 3 Volt Fast Boot Block Flash memory provides in-system programming and erase at 3.0 V– 3.6 V. For customers requiring fast programming in their manufacturing environment, this family of products includes an additional high-performance 12 V programming feature. The mode enhances programming performance during short period of time typically PP found in manufacturing processes ...
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... If a CPU reset occurs without a flash memory reset, proper CPU initialization will not occur because the flash memory may be providing status information instead of array data. Intel recommends connecting RST# to the system reset signal to allow proper CPU/flash initialization following system reset. ...
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... Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two- line control and proper de-coupling capacitor selection will suppress these transient voltage peaks. Each flash device should have a 0.1 µF ceramic capacitor connected between each V and between its placed as close as possible to the package leads ...
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... V connected for a total of 80 hours maximum. NOTICE: This datasheet contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before . finalizing a design Warning: Stressing the device beyond the “ ...
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Automotive Temperature Operating Conditions Symbol T Operating Temperature Supply Voltage CC1 CC V I/O Voltage CCQ Supply Voltage PP1 Supply Voltage PP2 PP Parameter Block Erase Cycling Cycling Main Block ...
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DC Characteristics—Automotive Temperature Sym Parameter I V Standby Current CCS Read Current CCR Program Current CCW Block Erase Current CCE Program Current PPW ...
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Figure 11. AC Input/Output Reference Waveform for V V CCQ 0V NOTE: AC test inputs are driven at 3.0 V for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends ...
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AC Characteristics—Read-Only Operations Automotive Temperature # Symbol Parameter R1 t CLK Period CLK CLK High (Low) Time CLK Fall (Rise) Time CHCL R4 t Address Valid Setup to CLK AVCH ...
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Figure 13. AC Waveform for CLK Input Figure 14. AC Waveform for Single Asynchronous Read Operations from Parameter Blocks, Status Register, Identifier Codes (A) 19 ADV# ( CE# (E) ...
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Figure 15. AC Waveform for Asynchronous Page Mode Read Operations from Main Blocks (A) 19 (A) 1 ADV# ( CE# ( ...
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Figure 16. AC Waveform for Single Synchronous Read Operations from Parameter Blocks, Status Register, Identifier Codes V IH CLK [ [A] 19 R17 V IH ADV# [ CE# [E] ...
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Figure 17. AC Waveform for Synchronous Burst Read Operations, Four-Word Burst Length, from Main Blocks V IH CLK ( (A) 19 ADV# ( CE# (E) V ...
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Figure 18. AC Waveform for Continuous Burst Read, Showing an Output Delay with Data Output Configuration Set to One Clock CLK (C) A (A) 19-0 ADV# (V) CE# (E) OE# (G) WE# (W) WAIT# (T) DQ (D/Q) 15-0 NOTES: 1. ...
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AC Characteristics—Write Operations Temperature # Sym RST# High Recovery to WE# (CE#) Going Low PHWL PHEL CE# (WE#) Setup to WE# (CE#) Going Low ELWL WLEL ...
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Figure 20. AC Waveform for Write Operations Note (A) 20 ADV# ( CE# (WE#) [E(W OE# [ WE# (CE#) [W(E)] ...
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AC Characteristics—Reset Operation—Automotive Temperature Figure 21. AC Waveform for Reset Operation RST ( (A) Reset while device is in read mode RST # (B) Reset during program or block ...
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Automotive Temperature Block Erase and Program Performance # Sym Program Time Block Program Time (Parameter) WHRH EHRH1 Block Program Time (Main) W19 Block Erase Time (Parameter WHRH EHRH2 Block Erase Time (Main) t ...
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... Ordering Information Package DE = Automotive temp., 56-Lead SSOP RA = Automotive temp., 56-Ball Easy BGA Product line designator ® for all Intel Flash products Device Density 800 = x16 (8-Mbit) Valid Combinations 56-Lead SSOP DE28F800F3T80 DE28F800F3B80 DE28F800F3T95 DE28F800F3B95 42 Access Speed (ns) (80,95 Top Blocking ...