TXC-04252AIPQ Transwitch Corporation, TXC-04252AIPQ Datasheet - Page 37

• Manufacturer Part Number: TXC-04252AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-04252AIPQ

• Pin Count: 160
• Screening Level: Industrial
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Notes:
1. All output times are measured with a maximum 75 pF load capacitance.
2. One SPcyc equals two EXTCK clock cycles.
3. Excessive external microprocessor data RAM access could interfere with the QE1M internal data processing, result-
A(10-0) address setup time to SEL
A(10-0) address hold time after WR
D(7-0) data input valid setup time to WR
D(7-0) data input hold time after WR
SEL setup time to WR
WR pulse width
RDY delay after SEL
RDY delay after WR
RDY float time after SEL
RDY pulse width
D(7-0) data valid setup
time to WR
(The EXTCK clock frequency is 58.32 MHz. One SPcyc is about 34.29 ns.)
ing in data corruption. To prevent such a situation, when excessive external microprocessor data RAM access is
detected, QE1M tries to slow down the external microprocessor access rate by lengthening the RDY pulse width to
as high as 97 * SPcyc.
(Output)
A(10-0)
(Input)
(Input)
(Input)
(Input)
D(7-0)
RDY
SEL
WR
Proprietary TranSwitch Corporation Information for use Solely by its Customers.
Parameter
Register write
SPOT instruction write (Note 2)
Data RAM write (Note 3)
SPOT instruction write and data
RAM write only
Figure 14. Microprocessor Write Cycle Timing - Intel
t
t
D(1)
SU(1)
t
SU(3)
Address
DATA SHEET
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t
SU(4)
t
SU(2)
Symbol
t
PW(2)
Data
t
t
t
t
t
t
t
t
PW(1)
D(2)
PW(1)
PW(2)
SU(1)
t
SU(2)
t
SU(3)
t
t
SU(4)
H(1)
H(2)
D(1)
D(2)
t
F
t
H(1)
-1 * SPcyc
5 * SPcyc
9 * SPcyc
Min
0.0
3.0
6.0
2.0
4.0
2.0
12
10
40
t
H(2)
Typ
29 * SPcyc
t
7 * SPcyc
F
Ed. 3, December 2000
Max
0.0
10
20
10
TXC-04252
TXC-04252-MB
QE1M
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns