TXC-04252AIPQ Transwitch Corporation, TXC-04252AIPQ Datasheet - Page 50

• Manufacturer Part Number: TXC-04252AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-04252AIPQ

• Pin Count: 160
• Screening Level: Industrial
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Ed. 3, December 2000
QE1M
TXC-04252
TXC-04252-MB
ADD BUS MULTIFRAME ALIGNMENT
When drop bus timing is selected, add bus V1 alignment is based on the drop bus V1 pulse (A/BDC1J1V1) if
DV1SEL is 1, or on the V1 reference signal that is generated by the H4 multiframe detectors in the drop bus
side if DV1SEL is 0.
When add bus timing is selected and a 0 is written to control bit DV1REF, V1 byte alignment for the add bus is
established by using the V1 pulses that must be present in the A/BAC1J1V1 signal. When add bus timing is
selected and a 1 is written to control bit DV1REF, V1 byte alignment for the add bus is determined by the drop
bus V1 reference from either the A/BDC1J1V1 signal (if DV1SEL is 1), or from the internal V1 reference signal
generated by the H4 multiframe detector in the drop bus direction (if DV1SEL is 0). The V1 pulse that is
present in the A/BAC1J1V1 signal is ignored. Extreme care must be taken when using this V1 selection mode
to prevent add bus V1 byte alignment slips.
The control bit selection for both V1 add and drop bus byte alignment is described in the table below.
Note: X = Don’t Care. Bus timing mode is selected via lead ABUST and control bits SBTEN, DRPBT, as described earlier.
Bus Timing Mode
Drop bus timing
Drop bus timing
Add bus timing
Add bus timing
Add bus timing
Add bus timing
selected
selected
selected
selected
selected
selected
Proprietary TranSwitch Corporation Information for use Solely by its Customers.
DV1REF
0
0
0
0
1
1
Add and Drop Bus V1 Reference Selection
DV1SEL
DATA SHEET
0
1
0
1
0
1
Drop bus A/B H4 multiframe detector determines dropped
TU/VT V1 byte starting location, and added TU/VT V1 byte
starting location. V1 pulse in drop bus A/BDC1J1V1 signal
ignored.
Drop bus V1 pulse in the A/BDC1J1V1 signal determines
dropped TU/VT V1 byte starting location, and added TU/VT
V1 byte starting location. A/B drop bus H4 multiframe detec-
tor disabled.
Drop bus A/B H4 multiframe detector determines dropped
TU/VT V1 byte starting location. V1 pulse in drop bus
A/BDC1J1V1 signal ignored. Add bus V1 alignment deter-
mined by the V1 pulse in the add bus A/BAC1J1V1 signal.
Drop bus V1 pulse in the A/BDC1J1V1 signal determines
dropped TU/VT starting location. Drop bus H4 multiframe
detector disabled. Add bus V1 alignment determined by the
V1 pulse in the add bus A/BAC1J1V1 signal.
Drop bus A/B H4 multiframe detector determines dropped
TU/VT V1 byte starting location. V1 pulses in drop bus
A/BDC1J1V1 and add bus A/BAC1J1V1 signals are
ignored. Add bus V1 alignment determined by the internal
V1 pulse generated by the drop bus A/B H4 byte detector.
Drop bus V1 pulse in the A/BDC1J1V1 signal determines
dropped TU/VT V1 byte starting location, A/B drop bus H4
multiframe detector disabled. V1 pulse in add bus
A/BAC1J1V1 signal is ignored. Add bus V1 alignment deter-
mined by the V1 pulse in the drop bus A/BDC1J1V1 signal.
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