LMX9830SM National Semiconductor, LMX9830SM Datasheet - Page 4

LMX9830SM

Manufacturer Part Number
LMX9830SM
Description
Manufacturer
National Semiconductor
Datasheet

Specifications of LMX9830SM

Lead Free Status / Rohs Status
Not Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LMX9830SM
Manufacturer:
NS/国半
Quantity:
20 000
www.national.com
OP7/SDA/
MDIDO
OP3/MWCS#
OP4/PG4
OP5
SCLK
SFS
SRD
STD
XOSCEN
PG6
PG7
CTS#(Note 3)
RXD
RTS#(Note 4)
TXD
RDY#
TCK
TDI
TDO
TMS
VCO_OUT
VCO_IN
ANT
VCC_PLL
VCC_CORE
VDD_X1
VDD_VCO
VDD_RF
VDD_IOR
VDD_IF
VCC_IOP
VCC_IO
VCC
GND_VCO
GND_RF
GND_IF
GND
NC
Note 2: Must use 1k Ω pull up.
Note 3: Connect to GND if CTS is not use.
Note 4: Treat as No Connect if RTS is not used. Pad required for mechanical stability.
Pad Name
Pad Location
B9, C10, E10
A1,A2,A3
B2,E2
D10
A10
F10
D4
D3
D6
E3
A6
A7
D2
C2
B3
B1
C3
A4
B4
B5
D5
A5
C5
E8
E6
A8
E4
C4
E1
E9
D7
F4
F1
F2
F3
F8
F9
F6
SDA/MDIDO: I/O
PG4: I/O
OP7: I
OP4: I
Type
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
GND (if not used)
See Table 16 and
See Table 16 and
See Table 16 and
NC (if not used)
Default Layout
See Table 16
Table 17
Table 17
Table 17
NC
NC
NC
NC
NC
NC
4
OP7: Pin checked during Startup Sequence for
configuration option
SDA: ACCESS.Bus Serial Data
MDIDO: SPI Master In Slave Out
OP3: Pin checked during Startup Sequence for
configuration option
MWCS#: SPI Slave Select Input (active low)
OP4: Pin checked during Startup Sequence for
configuration option
PG4: GPIO
OP5: Pin checked during Startup Sequence for
configuration option
Audio PCM Interface Clock
Audio PCM Interface Frame Synchronization
Audio PCM Interface Receive Data Input
Audio PCM Interface Transmit Data Output
Clock Request. Toggles with X2 (LP0) crystal enable/
disable
GPIO
GPIO - Default setup RF traffic LED indication
Host Serial Port Clear To Send (active low)
Host Serial Port Receive Data
Host Serial Port Request To Send (active low)
Host Serial Port Transmit Data
JTAG Ready Output (active low)
JTAG Test Clock Input
JTAG Test Data Input
JTAG Test Data Output
JTAG Test Mode Select Input
Charge Pump Output, connect to Loop filter
VCO Tuning Input, feedback from Loop filter
RF Antenna 50 Ω Nominal Impedance
1.8V Core Logic Power Supply Output
1.8V Voltage Regulator Output
Power Supply Crystal Oscillator
Power Supply VCO
Power Supply RF
Power Supply I/O Radio/BB
Power Supply IF
Power Supply Audio Interface
Power Supply I/O
Voltage Regulator Input
Ground
Ground
Ground
Ground
Treat as no connect. Place pad for mechanical stability
Description

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