MAX148BEAP Maxim Integrated Products, MAX148BEAP Datasheet - Page 13

• Manufacturer Part Number: MAX148BEAP
• Description: ADC (A/D Converters)
• Manufacturer: Maxim Integrated Products

Specifications of MAX148BEAP

• Number Of Adc Inputs: 8
• Architecture: SAR
• Conversion Rate: 133 KSPs
• Resolution: 10 bit
• Input Type: Voltage
• Interface Type: 4-Wire (SPI, QSPI, Microwire, TMS320)
• Voltage Reference: Internal 2.5 V or External
• Supply Voltage (max): 5 V
• Maximum Power Dissipation: 640 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-20
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: No

In internal clock mode, the MAX148/MAX149 generate
their own conversion clocks internally. This frees the FP
from the burden of running the SAR conversion clock
and allows the conversion results to be read back at
the processor’s convenience, at any clock rate from 0
to 2MHz. SSTRB goes low at the start of the conversion
and then goes high when the conversion is complete.
SSTRB is low for a maximum of 7.5Fs (SHDN = uncon-
nected), during which time SCLK should remain low for
best noise performance.
An internal register stores data when the conversion
is in progress. SCLK clocks the data out of this regis-
ter at any time after the conversion is complete. After
SSTRB goes high, the next falling clock edge produces
the MSB of the conversion at DOUT, followed by the
remaining bits in MSB-first format (Figure 9). CS does
Figure 9. Internal Clock Mode Timing
Figure 10. Internal Clock Mode SSTRB Detailed Timing
SSTRB
AD STATE
DOUT
SCLK
SSTRB
CS
DOUT
SCLK
______________________________________________________________________________________
DIN
CS
+2.7V to +5.25V, Low-Power, 8-Channel,
PD0 CLOCK IN
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
START
1
SEL2 SEL1 SEL0
2
t
CSH
3
IDLE
4
UNI/
BIP
5
SGL/
Internal Clock
DIF
t
ACQUISITION
SSTRB
6
(f
1.5Fs
PD1
SCLK
7
= 2MHz)(SHDN = UNCONNECTED)
PD0
8
t
CONV
CONVERSION
7.5Fs MAX
t
CONV
not need to be held low once a conversion is started.
Pulling CS high prevents data from being clocked into
the MAX148/MAX149 and three-states DOUT, but it
does not adversely affect an internal clock mode con-
version already in progress. When internal clock mode
is selected, SSTRB does not go into a high-impedance
state when CS goes high.
Figure 10 shows the SSTRB timing in internal clock
mode. In this mode, data can be shifted in and out of
the MAX148/MAX149 at clock rates exceeding 2.0MHz if
the minimum acquisition time (t
The falling edge of CS does not start a conversion. The
first logic high clocked into DIN is interpreted as a start
bit and defines the first bit of the control byte. A conver-
sion starts on SCLK’s falling edge, after the eighth bit of
9
MSB B8
B9
IDLE
10
11
B7
12
Serial 10-Bit ADCs
t
SCK
18
LSB S1
B0
19
20
t
CSS
S0
21
FILLED WITH
ZEROS
22
ACQ
23
t
D0
24
) is kept above 1.5Fs.
Data Framing
13