MAX148BEAP Maxim Integrated Products, MAX148BEAP Datasheet - Page 9

• Manufacturer Part Number: MAX148BEAP
• Description: ADC (A/D Converters)
• Manufacturer: Maxim Integrated Products

Specifications of MAX148BEAP

• Number Of Adc Inputs: 8
• Architecture: SAR
• Conversion Rate: 133 KSPs
• Resolution: 10 bit
• Input Type: Voltage
• Interface Type: 4-Wire (SPI, QSPI, Microwire, TMS320)
• Voltage Reference: Internal 2.5 V or External
• Supply Voltage (max): 5 V
• Maximum Power Dissipation: 640 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-20
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: No

allowed between conversions. The acquisition time,
t
the signal, and is also the minimum time needed for the
signal to be acquired. It is calculated by the following
equation:
where R
input signal, and t
source impedances below 4kI do not significantly affect
the ADC’s AC performance.
Higher source impedances can be used if a 0.01FF
capacitor is connected to the individual analog inputs.
Note that the input capacitor forms an RC filter with
the input source impedance, limiting the ADC’s signal
bandwidth.
The ADC’s input tracking circuitry has a 2.25MHz
small-signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate
by using undersampling techniques. To avoid high-
frequency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
Figure 5. Quick-Look Circuit
ACQ
OPTIONAL FOR MAX149,
REQUIRED FOR MAX148
, is the maximum time the device takes to acquire
MAX872
IN
+3V
COMP
= 9kI, R
V
OUT
t
ACQ
ANALOG
+2.500V
_______________________________________________________________________________________
ACQ
INPUT
*FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX)
+2.7V to +5.25V, Low-Power, 8-Channel,
= 7 x (R
0 TO
1000pF
S
is never less than 1.5Fs. Note that
0.01µF
= the source impedance of the
S
+3V
+ R
2.5V
C1
0.1µF
IN
CH7
REFADJ
VREF
) x 16pF
Input Bandwidth
MAX148
MAX149
SSTRB
SHDN
DGND
AGND
DOUT
SCLK
COM
V
DIN
CS
DD
N.C.
+3V
Internal protection diodes, which clamp the analog
input to V
swing from AGND - 0.3V to V
However, for accurate conversions near full scale, the
inputs must not exceed V
lower than AGND by 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of off
channels over 2mA.
To quickly evaluate the MAX148/MAX149’s analog per-
formance, use the circuit of Figure 5. The MAX148/
MAX149 require a control byte to be written to DIN
before each conversion. Tying DIN to +3V feeds in
control bytes of $FF (HEX), which trigger single-ended
unipolar conversions on CH7 in external clock mode
without powering down between conversions. In external
clock mode, the SSTRB output pulses high for one clock
period before the most significant bit of the conversion
result is shifted out of DOUT. Varying the analog input to
CH7 will alter the sequence of bits from DOUT. A total of
15 clock cycles is required per conversion. All transitions
of the SSTRB and DOUT outputs occur on the falling
edge of SCLK.
0.1µF
OSCILLATOR
+3V
DD
2MHz
Serial 10-Bit ADCs
and AGND, allow the channel input pins to
CH1
Analog Input Protection
CH2
DD
OSCILLOSCOPE
DD
by more than 50mV or be
+ 0.3V without damage.
CH3
Quick Look
CH4
SCLK
SSTRB
DOUT*
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