MAX148BEAP Maxim Integrated Products, MAX148BEAP Datasheet - Page 7

• Manufacturer Part Number: MAX148BEAP
• Description: ADC (A/D Converters)
• Manufacturer: Maxim Integrated Products

Specifications of MAX148BEAP

• Number Of Adc Inputs: 8
• Architecture: SAR
• Conversion Rate: 133 KSPs
• Resolution: 10 bit
• Input Type: Voltage
• Interface Type: 4-Wire (SPI, QSPI, Microwire, TMS320)
• Voltage Reference: Internal 2.5 V or External
• Supply Voltage (max): 5 V
• Maximum Power Dissipation: 640 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-20
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: No

Figure 1. Load Circuits for Enable Time
PIN
1–8
a) HIGH-Z TO V
10
11
12
13
14
15
16
17
18
19
20
9
DOUT
6kI
OH
DGND
CH0–CH7
AND V
REFADJ
SSTRB
NAME
DGND
SHDN
AGND
DOUT
SCLK
VREF
COM
_______________________________________________________________________________________
V
DIN
CS
+2.7V to +5.25V, Low-Power, 8-Channel,
DD
OL
TO V
C
50pF
LOAD
OH
Sampling Analog Inputs
Ground Reference for Analog Inputs. COM sets zero-code voltage in single-ended mode. Must be
stable to ±0.5 LSB.
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX148/MAX149 down; otherwise, they
are fully operational. Pulling SHDN high puts the reference-buffer amplifier in internal compensation
mode. Leaving SHDN unconnected puts the reference-buffer amplifier in external compensation
mode.
Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion.
In internal reference mode (MAX149 only), the reference buffer provides a 2.500V nominal output,
externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling
REFADJ to V
Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to V
Analog Ground
Digital Ground
Serial-Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high.
Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX148/MAX149 begin
the A/D conversion, and goes high when the conversion is finished. In external clock mode, SSTRB
pulses high for one clock period before the MSB decision. High impedance when CS is high
(external clock mode).
Serial-Data Input. Data is clocked in at SCLK’s rising edge.
Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT
is high impedance.
Serial-Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets
the conversion speed (duty cycle must be 40% to 60%).
Positive Supply Voltage
b) HIGH-Z TO V
DOUT
DD
V
OL
DD
AND V
.
6kI
DGND
C
50pF
LOAD
OH
TO V
OL
Figure 2. Load Circuits for Disable Time
FUNCTION
a) V
DOUT
OH
6kI
Serial 10-Bit ADCs
TO
HIGH-Z
DGND
C
50pF
LOAD
Pin Description
DOUT
b) V
OL
V
TO
DD
HIGH-Z
6kI
C
50pF
DGND
LOAD
DD
.
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