H5PS5162FFR-S6C HYNIX SEMICONDUCTOR, H5PS5162FFR-S6C Datasheet
H5PS5162FFR-S6C
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H5PS5162FFR-S6C Summary of contents
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... DDR2 SDRAM This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0 / Jul. 2008 H5PS5162FFR-xxC Series H5PS5162FFR-xxL Series H5PS5162FFR-xxI Series H5PS5162FFR Series 1 ...
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... Revision History Rev. 0.1 1.0 Rev. 1.0 / July. 2008 History Preliminary Release Release H5PS5162FFR series Draft Date Jan. 2008 Jul. 2008 2 ...
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... Differential AC output parameters 3.3 Output Buffer Levels 3.3.1 Output AC Test Conditions 3.3.2 Output DC Current Drive 3.3.3 OCD default characteristics 3.4 IDD Specifications & Measurement Conditions 3.5 Input/Output Capacitance 4. AC Timing Specifications 5. Package Dimensions Rev. 1.0 / July. 2008 Release H5PS5162FFR series 3 ...
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... Lead free materials. We'll add "R" character after "F" for Lead & Halogen free products. 3. H5PS5162FFR-XXC is commertial temp. and normal power 4. H5PS5162FFR-XXL is commertial temp. and low power 5. H5PS5162FFR-XXI is Industrial temp. and normal power Rev. 1.0 / July. 2008 Operating Frequency Speed Bin ...
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... NC E LDM F VDDQ DQ1 G DQ3 H VSS VREF CKE BA1 L BA0 A1 M A10 A12 H5PS5162FFR series VSSQ UDQS VDDQ UDQS VSSQ DQ15 VDDQ DQ8 VDDQ DQ10 VSSQ DQ13 VSSQ LDQS VDDQ LDQS VSSQ DQ7 VDDQ DQ0 VDDQ DQ2 VSSQ DQ5 VSSDL CK VDD ...
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... HIGH). If only one bank precharged, the bank is selected by BA0- BA1. The address inputs also provide the op code during MODE REGISTER SET com- mands. Input/ DQ Data input / output : Bi-directional data bus Output Rev. 1.0 / July. 2008 H5PS5162FFR series DESCRIPTION Release has REF REF 6 ...
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... Power Supply : 1.8V +/- 0.1V VSS Supply Ground VREF Supply Reference voltage for inputs for SSTL interface. Rev. 1.0 / July. 2008 DESCRIPTION x16 LDQS/LDQS and UDQS/UDQS "single-ended DQS signals" refers to any of the following with A10 = 1 x16 LDQS and UDQS Release H5PS5162FFR series -Continue- 7 ...
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... At tOPER 85~95℃, Double refresh rate(tREFI: 3.9us) is required, and to enter the self refresh mode at this tem- perature range it must be required an EMRS command to change itself refresh rate. Rev. 1.0 / July. 2008 - 2.3 V Parameter Normal Temp Industrial Temp Release H5PS5162FFR series Rating Units -55 to +100 ℃ ...
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... I (ac), V (ac), and VDDQ values defined in SSTL_18 (ac) V (ac Rtt(eff (ac) V (ac delta 100% VDDQ Release H5PS5162FFR series Units Max. 1.9 V 1.9 V 1.9 V 0.51*VDDQ mV VREF+0.04 V MIN NOM MAX UNITS NOTES ohm 120 150 180 ohm ohm -6 +6 ...
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... DDR2 400,533 Min. Max. VREF + - 0.250 - VREF - 0.250 Condition to V max for falling edges as shown in the below figure. IL(ac) delta TR max IL(ac) Rising Slew = H5PS5162FFR series Max. Units VDDQ + 0.3 V VREF - 0.125 V DDR2 667,800 Units Min. Max. VREF + - V 0.200 - VREF - 0.200 ...
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... VDDQ . VOX(AC) indicates the voltage at whitch differential output signals must cross. Rev. 1.0 / July. 2008 Min. 0.5 0.5 * VDDQ - 0.175 0.5 * VDDQ + 0.175 V DDQ SSQ < Differential signal levels > Min. 0.5 * VDDQ - 0.125 0.5 * VDDQ + 0.125 Release H5PS5162FFR series Max. Units Notes VDDQ + 0 Crossing point Max. Units Notes ...
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... V OUT DDQ OH /I must be less than 21 ohm for values of V OUT OL TT are based on the conditions given in Notes 1 and 2. They are used to test min plus a noise margin and V IH H5PS5162FFR series SSTL_18 Class II Units 0 DDQ SSTl_18 Units - 13.4 mA 13.4 mA ...
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... Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in tDQSQ and tQHS specification. Rev. 1.0 / July. 2008 Parameter Min See full strength default driver characteristics 0 0 Sout 1.5 VTT 25 ohms Reference Output point (Vout) Release H5PS5162FFR series Nom Max Unit Notes ohms 1 1.5 ohms 6 4 ohms 1,2 V/ns 1,4,5,6,7,8 13 ...
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... Symbol IDD0 IDD1 IDD2P IDD2Q IDD2N F IDD3P S IDD3N IDD4W IDD4R IDD5B Normal Power IDD6 Low Power* IDD7 Note: 1. Low power parts have an extra suffix "L" in part number ; ex) H5PS5162FFR-xxL series Rev. 1.0 / July. 2008 DDR2 667 x16 x16 120 110 130 120 ...
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... ING; Data bus inputs are SWITCHING Self refresh current; CK and CK at 0V; CKE £ 0.2V; Other control and address bus inputs are IDD6 FLOATING; Data bus inputs are FLOATING Rev. 1.0 / July. 2008 H5PS5162FFR series Conditions Fast PDN Exit MRS(12 Slow PDN Exit MRS(12 Release ...
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... SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes. Rev. 1.0 / July. 2008 Release H5PS5162FFR series mA 16 ...
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... A0 RA0 RA1 RA2 RA3 (23 clocks) -DDR2-800 6/6/6: A0 RA0 RA1 RA2 RA3 (24 clocks) Rev. 1.0 / July. 2008 DDR2-800 DDR2-667 5-5-5 6-6-6 5-5 12 57. 2.5 2 70000 70000 70000 12 105 105 105 Release H5PS5162FFR series DDR2-533 DDR2-400 4-4-4 3-3 3. 70000 70000 15 15 105 105 Units tCK ...
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... CASE ≤ 95℃ 3.9 85℃ < T CASE DDR2-800E DDR2-667D 6-6-6 5-5-5 min min Release H5PS5162FFR series DDR2 667 DDR2 800 Min Max Min Max 1.0 2.0 1.0 2.0 x 0.25 x 0.25 1.0 2.0 1.0 1.75 x 0.25 x 0.25 2.5 3.5 2 ...
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... Release H5PS5162FFR series DDR2-533 Unit Note min max -500 +500 ps -450 +450 ps 0.45 0.55 tCK 0.45 0.55 tCK min - ps 11,12 (tCL,tCH) 3750 8000 ps 6,7,8, ...
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... AONPD 2.5 2.5 AOFD tAC(max) t tAC(min) AOF + 0.6 2.5tCK+ tAC(min)+ t tAC(max) AOFPD 2 +1 tANPD 3 tAXPD 8 tOIT 0 12 tIS+tCK+t tDelay IH Release H5PS5162FFR series -Continue- DDR2-533 Unit Note min max 0.9 1.1 tCK 0.4 0.6 tCK 7 37 tCK WR+tRP - tCK 7.5 ...
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... Release H5PS5162FFR series DDR2-800 Unit Note min max -400 +400 ps -350 +350 ps 0.45 0.55 tCK 0.45 0.55 tCK min(tCL 11,12 tCH) 2500 ps 6,7,8,2 ...
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... AONPD tAC(max)+1 t 2.5 2.5 AOFD tAC(max)+ t tAC(min) AOF 0.6 tAC(min) 2.5tCK+ t AOFPD +2 tAC(max)+1 tANPD 3 tAXPD 8 tOIT 0 12 tIS+tCK+tI tDelay H Release H5PS5162FFR series -Continue- DDR2-800 Unit Note min max ns 37 tCK WR+tRP - tCK 14 7 7.5 ns tRFC + ns 10 200 - ...
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... DDR2 SDRAM pin timings are measured is mode dependent. In single Rev. 1.0 / July. 2008 DQ DQS Output DQS RDQS Timing RDQS 25 reference point AC Timing Reference Load DQ Output DQS, DQS Ω 25 Test point Slew Rate Test Load H5PS5162FFR series DDQ Ω DDQ Release 23 ...
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... Rev. 1.0 / July. 2008 t t DQSH DQSL DQS DQS t WPRE V V (ac (ac (ac) IH DMin DMin DMin V (ac) IL Figure -- Data input (write) timing RPRE DQSQmax t QH Figure -- Data output (read) timing H5PS5162FFR series t WPST (dc (dc (dc) IH DMin V (dc RPST DQSQmax t QH Release 24 ...
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... V/ns 1.8 V/ns 1.6 V/ns △ tD △ tD △ tD △ tD △ tD △ +125 + +83 + -14 -11 - -25 -31 -13 - -31 - H5PS5162FFR series 1.4 V/ns 1.2 V/ns 1.0 V/ns △ tD △ tD △ tD △ tD △ tD △ - -59 -31 -47 -19 - -74 -89 -62 -77 - -127 -140 -115 -128 -103 -116 Release 0 ...
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... IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac). For slew rate in between the values listed in table x, the derating valued may obtained by linear interpolation. These values are typically not subject to production test. They are verified by design and characterization. Rev. 1.0 / July. 2008 Release H5PS5162FFR series 26 ...
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... REF V (dc)max IL V (ac)max IL Vss Delta TF Setup Slew Rate V REF = Falling Signal Rev. 1.0 / July. 2008 nominal slew rate Delta TR (dc)-V (ac)max Setup Slew Rate IL Rising Signal Delta TF Release H5PS5162FFR series nominal slew rate REF region V (ac)min-V (dc) REF IH = Delta TR 27 ...
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... Vss Delta TF Setup Slew Rate Tangent line[V = Falling Signal Rev. 1.0 / July. 2008 nominal line Tangent line Delta TR Setup Slew Rate Tangent line[V = Rising Signal (dc)-V (ac)max] REF IL Delta TF Release H5PS5162FFR series tangent line REF region (ac)min-V (dc)] REF IH Delta TR 28 ...
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... REF V (dc)max IL V (ac)max IL Vss V Hold Slew Rate REF = Rising Signal Rev. 1.0 / July. 2008 nominal slew rate Delta TR (dc)-V (dc)max Hold Slew Rate IL Falling Signal Delta TR Release H5PS5162FFR series nominal slew rate Delta TF V (dc)min - V (dc) IH REF = Delta TF 29 ...
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... IL Vss Hold Slew Rate Tangent line[V = Rising Signal Rev. 1.0 / July. 2008 Tangent nominal line line Delta TR (dc)-V (ac)max] REF IL Delta TR Hold Slew Rate = Falling Signal Release H5PS5162FFR series nominal line tangent line Delta TF Tangent line[V (ac)min-V (dc)] REF IH Delta TF 30 ...
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... Release H5PS5162FFR series 1.0 V/ns △tIS △tIH Units Notes +247 +124 ps 1 +239 +149 ps 1 +227 +143 ps 1 +210 +135 ps 1 +185 ...
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... REF (dc). If the actual signal is always later than the nominal slew rate REF (dc) region’, use nominal slew rate for derating value(see Fig.c) If the actual REF H5PS5162FFR series (ac)max. If the actual signal is IL (dc region’, use nominal slew REF (dc) region’, the slew ...
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... Rev. 1.0 / July. 2008 VOH + xmV VTT + 2xmV VOH + 2xmV VTT + xmV VOL + 1xmV VTT -xmV VOL + 2xmV VTT - 2xmV tLZ , tRPRE begin point = 2*T1-T2 (ac) level to the differential data strobe crosspoint for a falling signal IL Release H5PS5162FFR series tLZ tRPRE begin point T1 T2 (dc ...
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... Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 x tCK + tIH. Rev. 1.0 / July. 2008 Differential Input waveform timing tDS tDH tDS tDH Release H5PS5162FFR series V DDQ V min IH(ac) V min IH(dc) V ...
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... Input clock jitter spec parameter. These parameters and the ones in the table below are referred to as 'input clock jitter spec parameters' and these parameters apply to DDR2-667 and DDR2-800 only. The jitter specified is a random jitter meeting a Gaussian distribution. Rev. 1.0 / July. 2008 Release H5PS5162FFR series 35 ...
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... Symbol min tCK(abs) tCK(avg),min+tJIT(per),min tCH(avg),min*tCK(avg),min+tJIT( tCH(abs) per),min tCL(avg),min*tCK(avg),min+tJIT( tCL(abs) per),min H5PS5162FFR series DDR2-800 Units max min max 125 -100 100 ps 100 - 250 -200 200 ps 200 ...
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... For example, if the measured jitter into a DDR2-667 SDRAM has tJIT(duty),min = - 72 ps and tJIT(duty),max = + 93 ps, then tRPST,min(derated) = tRPST,min + tJIT(duty),min = 0.4 x tCK(avg 928 ps and tRPST,max(derated) = tRPST,max + tJIT(duty),max = 0.6 x tCK(avg 1592 ps. (Caution on the min/max usage!) Rev. 1.0 / July. 2008 Release H5PS5162FFR series 37 ...
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... However tAC values used in the equations shown above are from the timing parameter table and are not derated. Thus the final derated values for tAOF are; tAOF,min(derated_final) = tAOF,min(derated tJIT(duty),max - tERR(6-10per),max } tAOF,max(derated_final) = tAOF,max(derated tJIT(duty),min - tERR(6-10per),min } Rev. 1.0 / July. 2008 Release H5PS5162FFR series 38 ...
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... Package Dimension(x16) 84Ball Fine Pitch Ball Grid Array Outline A1 Ball Mark A1 Ball Mark 1 2 0.80 Rev. 1.0 / July. 2008 8.0 +/- 0.10 <Top View> φ0.45 ± 6.40 <Bottom View> note: all dimension units are Millimeters. Release H5PS5162FFR series 1.20 Max. 0.34 +/- 0.05 39 ...