H5PS5162FFR-S6C HYNIX SEMICONDUCTOR, H5PS5162FFR-S6C Datasheet - Page 24
H5PS5162FFR-S6C
Manufacturer Part Number
H5PS5162FFR-S6C
Description
58T1896
Manufacturer
HYNIX SEMICONDUCTOR
Datasheet
1.H5PS5162FFR-S6C.pdf
(39 pages)
Specifications of H5PS5162FFR-S6C
Memory Type
SDRAM
Memory Configuration
32M X 16
Memory Case Style
FBGA
No. Of Pins
84
Operating Temperature Range
0°C To +85°C
Memory Size
512 Mbit
Voltage Vcc
1.8V
Rohs Compliant
Yes
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Rev. 1.0 / July. 2008
VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its comple-
ment, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that when differen-
tial data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally to VSS through a
20 ohm to 10 K ohm resistor to insure proper operation.
5. AC timings are for linear signal transitions. See System Derating for other signal transitions.
6. These parameters guarantee device behavior, but they are not necessarily tested on each device.
7. All voltages referenced to VSS.
8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/
They may be guaranteed by device design or tester correlation.
supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage
range specified.
CK/CK
DQS/DQS
DQ
DQS/
DQS
DQ
DM
CK
CK
DQS
DQS
t
CH
t
t
RPRE
DQS
DQS
WPRE
Figure -- Data output (read) timing
V
V
IL
IH
(ac)
(ac)
t
DMin
DS
t
t
CL
DQSQmax
D
Figure -- Data input (write) timing
t
DQSH
V
V
IH
IL
(ac)
(ac)
t
DMin
t
DS
QH
D
Q
t
DQSL
DMin
Q
D
t
DH
V
IH
V
(dc)
IL
(dc)
t
DQSQmax
DMin
Q
V
D
t
IL
DH
(dc)
V
IH
t
WPST
(dc)
H5PS5162FFR series
t
t
RPST
QH
Q
Release
24