ADC1005CCJ National Semiconductor, ADC1005CCJ Datasheet - Page 8

• Manufacturer Part Number: ADC1005CCJ
• Description: ADC Single SAR 10-Bit Parallel 20-Pin CDIP
• Manufacturer: National Semiconductor

Specifications of ADC1005CCJ

• Package: 20CDIP
• Resolution: 10 Bit
• Architecture: SAR
• Number Of Analog Inputs: 1
• Differential Input: Yes
• Digital Interface Type: Parallel
• Input Type: Voltage
• Polarity Of Input Voltage: Unipolar

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Block Diagram
Note 9: CS shown twice for clarity.
Note 10: SAR=Successive Approximation Register.
Functional Description
1.0 GENERAL OPERATION
A block diagram of the A/D converter is shown in
of the inputs and outputs are shown and the major logic con-
trol paths are drawn in heavier weight lines.
1.1 Converter Operation
The ADC1005 uses an advanced potentiometric resistive lad-
der network. The analog inputs, as well as the taps of this
ladder network are switched into a weighted capacitor array.
The output of this capacitor array is the input to a sampled
data comparator. This comparator allows the successive ap-
proximation logic to match the analog input voltage [V
V
tested first and after 10 comparisons (80 clock cycles) a digital
10-bit binary code (all “1”s = full-scale) is transferred to an
output latch.
IN
(−)] to taps on the R network. The most significant bit is
5261 Version 8 Revision 2
Figure
IN
1. All
(+) –
FIGURE 1.
Print Date/Time: 2009/08/26 22:47:16
8
1.2 Starting a Conversion
The conversion is initialized by taking CS and WR simultane-
ously low. This sets the start flip-flop (F/F) and the resulting
“1” level resets the 10-bit shift register, resets the interrupt
(INTR) F/F and inputs a “1” to the D flop, F/F1, which is at the
input end of the 10-bit shift register. Internal clock signals then
transfer this “1” to the Q output of F/F1. The AND gate, G1,
combines this “1” output with a clock signal to provide a reset
signal to the start F/F. If the set signal is no longer present
(either WR or CS is a “1”) the start F/F is reset and the 10-bit
shift register then can have the “1” clocked in, allowing the
conversion process to continue. If the set signal were still
present, this reset pulse would have no effect and the 10-bit
shift register would continue to be held in the reset mode. This
logic therefore allows for wide CS and WR signals. The con-
verter will start after at least one of these signals returns high
and the internal clocks again provide a reset signal for the
start F/F.
To summarize, on the high-to-low transition of the WR input
the internal SAR latches and the shift register stages are re-
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