TE28F800C3TA90 Intel, TE28F800C3TA90 Datasheet - Page 33

• Manufacturer Part Number: TE28F800C3TA90
• Description: Flash Mem Parallel 3V/3.3V 8M-Bit 512K x 16 90ns 48-Pin TSOP
• Manufacturer: Intel

Specifications of TE28F800C3TA90

• Package: 48TSOP
• Density: 8 Mb
• Architecture: Sectored
• Block Organization: Asymmetrical
• Location Of Boot Block: Top
• Typical Operating Supply Voltage: 3|3.3 V
• Sector Size: 8KByte x 8|64KByte x 15
• Support Of Common Flash Interface: Yes
• Timing Type: Asynchronous
• Operating Temperature: -40 to 85 °C
• Interface Type: Parallel

6.5
6.5.1
6.5.2
6.5.3
Datasheet
During program or erase modes, RP# transitioning low will abort the in-progress operation. The
memory contents of the address being programmed or the block being erased are no longer valid as
the data integrity has been compromised by the abort. During deep power-down, all internal
circuits are switched to a low-power savings mode (RP# transitioning to V
to the device clears the status register).
Power and Reset Considerations
Power-Up/Down Characteristics
In order to prevent any condition that may result in a spurious write or erase operation, it is
recommended to power-up VCC and VCCQ together. Conversely, VCC and VCCQ must power-
down together.
It is also recommended to power-up VPP with or after VCC has reached VCC
must powerdown with or slightly before VCC.
If VCCQ and/or VPP are not connected to the VCC supply, then VCC should attain VCC
applying VCCQ and VPP. Device inputs should not be driven before supply voltage reaches
VCC
Power supply transitions should only occur when RP# is low.
RP# Connected to System Reset
The use of RP# during system reset is important with automated program/erase devices since the
system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs
without a flash memory reset, proper CPU initialization will not occur because the flash memory
may be providing status information instead of array data. Intel recommends connecting RP# to the
system CPU RESET# signal to allow proper CPU/flash initialization following system reset.
System designers must guard against spurious writes when V
both WE# and CE# must be low for a command write, driving either signal to V
writes to the device. The CUI architecture provides additional protection since alteration of
memory contents can only occur after successful completion of the two-step command sequences.
The device is also disabled until RP# is brought to V
By holding the device in reset during power-up/down, invalid bus conditions during power-up can
be masked, providing yet another level of memory protection.
V
The CUI latches commands as issued by system software and is not altered by V
transitions or WSM actions. Its default state upon power-up, after exit from reset mode or after
V
After any program or Block-Erase operation is complete (even after V
V
flash-memory array is desired.
CC
PPLK
CC
min
transitions above V
, V
), the CUI must be reset to read-array mode via the Read Array command if access to the
.
PP
and RP# Transitions
LKO
(Lockout voltage), is read-array mode.
Intel
£
Advanced+ Boot Block Flash Memory (C3)
IH
, regardless of the state of its control inputs.
CC
voltages are above V
PP
transitions down to
IL
min
or turning off power
. Conversely, VPP
IH
PP
will inhibit
or CE#
LKO
min
. Because
before
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