UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 373

• Manufacturer Part Number: UPD78F0034BGC-8BS-A
• Description: MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034BGC-8BS-A

• Package: 64LQFP
• Family Name: 78K0
• Maximum Speed: 12 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 51
• Interface Type: 3-Wire/UART
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

Remark While the slave is outputting a low level to the data line, the master cannot issue the stop condition. This
happens if EEPROM is not reset, even though the microcontroller is reset, because of supply voltage
fluctuation during communication (reading from EEPROM). In this case, the EEPROM continues
sending data, and may output a low level to the data line. Because the structure of I
the master to forcibly make the data line high, the master cannot issue the stop condition.
To avoid this phenomenon, it is possible to use a clock line as a port, output a dummy clock from the
port, continue reading data from EEPROM by inputting the dummy clock, and complete reading with
some EEPROMs (because the data line goes high when reading is completed, the master can issue
the stop condition. After that, the status of EEPROM can be controlled). At this time, the port
corresponding to the data line must always be in the high-impedance state (high-level output).
CHAPTER 18 SERIAL INTERFACE IIC0 ( PD780024AY, 780034AY SUBSERIES ONLY)
Yes
ACKE0 = 0, WREL0 = WTIM0 = 1
Re-set IIC control register 0.
Re-set IIC control register 0.
ACKE0 = 1, WTIM0 = 0
Start data reception.
Issue stop condition.
Save receive data.
Remaining data?
Clear INTIIC0.
IIC0
INTIIC0 = 1?
INTIIC0 = 1?
SPD0 = 1?
SPT0 = 1
END
D
0FFH
No
Yes
Yes
Yes
Figure 18-21. Master Operation Flowchart (5/5)
No
No
No
User’s Manual U14046EJ5V0UD
Set so that ACK is automatically returned
after an 8-clock wait (set ACKE0 so that
ACK is returned except when the last data
is received. Specify an 8-clock wait so that
automatic returning of ACK can be cleared
when the last data is received).
Write dummy data to IIC0 and start
reception (reception can also be started
when WREL0 = 1).
Reception is completed when INTIIC0
occurs.
Save the received data to a buffer.
When reception of data is completed,
disable automatic returning of ACK, set a 9-
clock wait, cancel wait in the ACK cycle,
and stop at the 9th clock. As a result, ACK
is not returned to the slave. This indicates
the completion of reception. Issue the stop
condition and end communication.
2
C does not allow
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