UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 476

• Manufacturer Part Number: UPD78F0034BGC-8BS-A
• Description: MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034BGC-8BS-A

• Package: 64LQFP
• Family Name: 78K0
• Maximum Speed: 12 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 51
• Interface Type: 3-Wire/UART
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

474
Instruction Mnemonic
16-bit
data
transfer
8-bit
operation
Group
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
2. When an area except the internal high-speed RAM area is accessed
3. Only when rp = BC, DE or HL
4. Except r = A
MOVW
XCHW
ADD
ADDC
2. This clock cycle applies to internal ROM program.
3. n is the number of waits when external memory expansion area is read from.
4. m is the number of waits when external memory expansion area is written to.
register (PCC).
rp, #word
saddrp, #word
sfrp, #word
AX, saddrp
saddrp, AX
AX, sfrp
sfrp, AX
AX, rp
rp, AX
AX, !addr16
!addr16, AX
AX, rp
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
Operands
Note 3
Note 3
Note 3
Note 4
Note 4
CHAPTER 24 INSTRUCTION SET
User’s Manual U14046EJ5V0UD
Byte
3
4
4
2
2
2
2
1
1
3
3
1
2
3
2
2
2
3
1
2
2
2
2
3
2
2
2
3
1
2
2
2
Note 1
10
10
6
8
–
6
6
–
–
4
4
4
4
6
4
4
4
8
4
8
8
8
4
6
4
4
4
8
4
8
8
8
Clock
12 + 2m (addr16)
12 + 2n AX
Note 2
9 + n
5 + n
9 + n
9 + n
9 + n
9 + n
5 + n
9 + n
9 + n
9 + n
10
10
–
8
8
8
8
–
–
–
–
8
–
–
5
–
8
–
–
5
rp
(saddrp)
sfrp
AX
(saddrp)
AX
sfrp
AX
rp
AX
A, CY
(saddr), CY
A, CY
r, CY
A, CY
A, CY
A, CY
A, CY
A, CY
A, CY
A, CY
(saddr), CY
A, CY
r, CY
A, CY
A, CY
A, CY
A, CY
A, CY
A, CY
word
AX
(saddrp)
sfrp
rp
(addr16)
rp
word
AX
CPU
r + A
r + A + CY
A + byte
A + r
A + (saddr)
A + (addr16)
A + (HL)
A + (HL + byte)
A + (HL + B)
A + (HL + C)
A + byte + CY
A + r + CY
A + (saddr) + CY
A + (addr16) + CY
A + (HL) + CY
A + (HL + byte) + CY
A + (HL + B) + CY
A + (HL + C) + CY
) selected by the processor clock control
word
AX
AX
(saddr) + byte
(saddr) + byte + CY
Operation
Z AC CY
Flag