ZL50110GAG Zarlink, ZL50110GAG Datasheet

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... Copyright 2003-2009, Zarlink Semiconductor Inc. All Rights Reserved. 128, 256, 512 and 1024 Channel CESoP ZL50110GAG ZL50111GAG ZL50112GAG ZL50114GAG ZL50110GAG2 552 PBGA** Trays, Bake & Drypack ZL50111GAG2 ZL50112GAG2 552 PBGA** Trays, Bake & Drypack ZL50114GAG2 552 PBGA** Trays, Bake & Drypack • Dual reference Stratum 4 and 4E DPLL for ...

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... Leased Line support over packet networks • Multi-Tenant Unit access concentration • TDM over Cable • Fibre To The Premises G/E-PON • Layer 2 VPN services • Customer-premise and Provider Edge Routers and Switches • Packet switched backplane applications ZL50110/11/12/14 2 Zarlink Semiconductor Inc. Data Sheet ...

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... This reduces system costs and simplifies the design. For applications that do require more memory (e.g., high stream count or high latency), the device supports Mbytes of SSRAM. A comprehensive evaluation system is available upon request from your local Zarlink representative or distributor. This system includes the CESoP processor, various TDM interfaces and a fully featured evaluation software GUI that runs on a Windows PC ...

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... Dual Redundant 1000 Mbps GMII/TBI or Single 100 Mbps MII and Single 1000 Mbps GMII/TBI Triple 100 Mbps MII or Dual Redundant 1000 Mbps GMII/TBI or Single 100 Mbps MII and Single 1000 Mbps GMII/TBI 4 Zarlink Semiconductor Inc. Data Sheet Notes Note 1 Note 1 Note 1 Note 1 ...

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... Unstructured Payload Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.5 Protocol Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.6 Packet Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.7 Packet Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.8 TDM Formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.0 Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.1 Differential Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.2 Adaptive Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.3 SYSTEM_CLK Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.0 System Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 ZL50110/11/12/14 Table of Contents 5 Zarlink Semiconductor Inc. Data Sheet ...

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... TDM Interface Timing - H.110 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 11.3 TDM Interface Timing - H-MVIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 11.4 TDM LIU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 11.5 PAC Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 11.6 Packet Interface Timing 11.6.1 MII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 11.6.2 MII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 11.6.3 GMII Transmit Timing ZL50110/11/12/14 Table of Contents 6 Zarlink Semiconductor Inc. Data Sheet ...

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... TDM Interface - special considerations during layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 13.1.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 13.2 CPU TA Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 13.3 Mx_LINKUP_LED Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 14.0 Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 14.1 External Standards/Specifications 109 14.2 Zarlink Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 15.0 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 ZL50110/11/12/14 Table of Contents 7 Zarlink Semiconductor Inc. Data Sheet ...

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... Figure 42 - External RAM Read and Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Figure 43 - CPU Read - MPC8260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Figure 44 - CPU Write - MPC8260 Figure 45 - CPU DMA Read - MPC8260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Figure 46 - CPU DMA Write - MPC8260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Figure 47 - JTAG Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Figure 48 - JTAG Clock and Reset Timing 102 ZL50110/11/12/14 List of Figures 8 Zarlink Semiconductor Inc. Data Sheet ...

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... Figure 49 - ZL50110/11/12/14 Power Consumption Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Figure 50 - CPU_TA Board Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Figure 51 - Mx_LINKUP_LED Stuffing Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 ZL50110/11/12/14 List of Figures 9 Zarlink Semiconductor Inc. Data Sheet ...

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... Table 40 - MAC Management Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 41 - External Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 42 - CPU Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Table 43 - System Clock Timing 100 Table 44 - JTAG Interface Timing 101 Table 45 - Mx_LINKUP_LED Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table 46 - Mx_LINKUP_LED Stuffing Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 ZL50110/11/12/14 List of Tables 10 Zarlink Semiconductor Inc. Data Sheet ...

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... Add a note about jumbo packets Include a paragraph to clarify the support for structure and unstructure modes at the same time Include more detailed description for the Payload Assembly Add a note at the end of the section Include more detailed description for the TDM formatter 11 Zarlink Semiconductor Inc. Data Sheet ...

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... Inverted polarity of CPU_DREQ0 and CPU_DREQ1 to conform with default MPC8260. Polarity of CPU_DREQ and CPU_SDACK remains programmable through API. Inverted polarity of CPU_DREQ0 and CPU_DREQ1 to conform with default MPC8260. Polarity of CPU_DREQ and CPU_SDACK remains programmable through API. 12 Zarlink Semiconductor Inc. Data Sheet ...

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... DC Electrical Characteristics Table and Output Levels Table 98 Section 13.3 ZL50110/11/12/14 Change Added 5 kohm pulldown recommendation to GPIO signals. Change Corrected Mx_LINKUP_LED pin assignment. Changed Electrical Characteristics to differentiate between 3.3 V and 5 V tolerant signals. New section added; Mx_LINKUP_LED Outputs. 13 Zarlink Semiconductor Inc. Data Sheet ...

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... Physical Specification The ZL50110/11/12/14 is packaged in a PBGA device. Features: • Body Size: • Ball Count: • Ball Pitch: • Ball Matrix: • Ball Diameter: • Total Package Thickness: ZL50110/11/12/ (typ) 552 1.27 mm (typ 0.75 mm (typ) 2.33 mm (typ) 14 Zarlink Semiconductor Inc. Data Sheet ...

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... R[8] R[13] R[18] R[20] ALE Q1 CPU_ADD CPU_ADD CPU_ADD GND CPU_CS CPU_SDA IC_VDD_I CPU_IRE CPU_DAT R[5] R[10] R[15] R[19] CK1 Zarlink Semiconductor Inc. Data Sheet TDM_STi[ TDM_CLKi TDM_STi[ TDM_STo[ TDM_STi[ TDM_CLK TDM_CLK GND o[18] 18] [20] 20] 21] 21] o[24] o[25] TDM_CLK TDM_STo[ TDM_STo[ TDM_CLK ...

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... R[18] R[20] ALE Q1 CPU_ADD CPU_ADD CPU_ADD GND CPU_CS CPU_SDA IC_VDD_I CPU_IRE CPU_DAT R[5] R[10] R[15] R[19] CK1 Zarlink Semiconductor Inc. Data Sheet N/C N/C N/C N/C N/C N/C N/C GND Ko[0] N/C N/C N/C N/C N/C N/C N/C N/C Ki[0] N/C ...

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... DR[20] ALE EQ1 A[4] CPU_AD CPU_AD CPU_AD GND CPU_CS CPU_SD IC_VDD_I CPU_IRE CPU_DAT DR[5] DR[10] DR[15] DR[19] ACK1 O Q0 A[0] 17 Zarlink Semiconductor Inc. Data Sheet A N/C N/C N/C N/C N/C N/C N/C GND B N/C N/C N/C N/C N/C N/C N/C N/C C ...

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... DR[13] DR[18] DR[20] ALE EQ1 CPU_AD CPU_AD CPU_AD GND CPU_CS CPU_SD IC_VDD_I CPU_IRE DR[5] DR[10] DR[15] DR[19] ACK1 Zarlink Semiconductor Inc. Data Sheet N/C N/C N/C N/C N/C N/C N/C N/C GND N/C N/C N/C N/C N/C N/C N/C N/C N/C ...

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... C15 TDM_CLKo[16] * C16 TDM_STi[16] * C17 TDM_CLKo[17] * C18 TDM_STi[19] * C19 TDM_CLKo[21] * C20 TDM_CLKi[21] * C21 TDM_CLKi[24] * C22 TDM_STi[22] * C23 TDM_STo[26] 19 Zarlink Semiconductor Inc. Data Sheet Ball Signal Name Number * C24 TDM_CLKi[27] * C25 TDM_STi[27] * C26 TDM_STi[28] D1 RAM_DATA[3] D2 RAM_DATA[1] D3 TDM_CLKiS D4 RAM_DATA[0] D5 TDM_STi[0] D6 TDM_CLKi[1] D7 TDM_STo[3] ‡ ...

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... H25 M3_TXCLK * H26 M3_RXER J1 RAM_DATA[29] J2 RAM_DATA[28] J3 RAM_DATA[27] J4 RAM_DATA[26] J5 RAM_DATA[22] J6 RAM_DATA[20] J9 VDD_IO J10 VDD_IO J11 VDD_IO 20 Zarlink Semiconductor Inc. Data Sheet Ball Signal Name Number J12 VDD_IO J13 VDD_IO J14 VDD_IO J15 VDD_IO J16 VDD_IO J17 VDD_IO J18 VDD_IO * J21 M3_RXDV * J22 ...

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... P23 M1_TXEN P24 GND P25 M1_RXD[4] P26 M1_RXD[6] R1 RAM_ADDR[12] R2 RAM_ADDR[14] R3 RAM_ADDR[15] R4 RAM_ADDR[19] R5 IC_GND VDD_IO 21 Zarlink Semiconductor Inc. Data Sheet Ball Signal Name Number R11 GND R12 GND R13 GND R14 GND R15 GND R16 GND R18 VDD_IO R21 M1_TXD[0] R22 M1_TXD[3] ...

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... AA14 VDD_CORE AA15 CPU_DATA[8] AA16 CPU_DATA[15] AA17 CPU_DATA[23] AA18 VDD_CORE † AA19 M2_RXCLK † AA20 M2_RXDV AA21 GND 22 Zarlink Semiconductor Inc. Data Sheet Ball Signal Name Number AA22 M0_TXD[0] AA23 M0_TXD[3] AA24 M0_REFCLK AA25 M0_RBC1 AA26 M0_RXD[0] AB1 GPIO[5] AB2 GPIO[11] ...

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... AE24 M2_TXD[0] † AE25 M2_TXD[3] † AE26 M2_COL AF1 GND AF2 RAM_DATA[50] AF3 RAM_DATA[55] AF4 RAM_DATA[56] AF5 RAM_DATA[61] 23 Zarlink Semiconductor Inc. Data Sheet Ball Signal Name Number AF6 TEST_MODE[2] AF7 JTAG_TDI AF8 IC_GND AF9 CPU_ADDR[5] AF10 CPU_ADDR[10] AF11 CPU_ADDR[15] AF12 CPU_ADDR[19] ...

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... C22 [6] A6 per stream. Streams [7:0] are used for J2, A23 [5] D8 and streams [1:0] are used for T3 and E3. A21 [4] B5 C18 [3] C5 A19 [2] B3 B17 [1] E9 C16 [ Zarlink Semiconductor Inc. Data Sheet Description TDM_D[31:0] ...

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... MHz or 44.736 MHz depending on [10] A10 standard used. At 8.192 Mbps only streams [9] B9 [7:0] are used. Streams [7:0] are used for [8] E12 J2, and streams [1:0] are used for T3 and [7] C8 E3. [6] C7 [5] D9 [4] E10 [3] B4 [2] F10 [ Zarlink Semiconductor Inc. Data Sheet Description TDM_D[31:0] ...

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... C11 Triggered on rising edge or falling edge [8] D11 depending on standard. At 8.192 Mbps only [7] A8 streams [3:0] are used, with 128 channels [6] A6 per stream. Streams [3:0] are used for J2. [5] D8 [4] B5 [3] C5 [2] B3 [ Zarlink Semiconductor Inc. Data Sheet Description Description TDM_D[15:0] ...

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... MHz, 8.192 MHz, 16.384 MHz, [11] A11 34.368 MHz or 44.736 MHz depending on [10] A10 standard used. At 8.192 Mbps only streams [9] B9 [3:0] are used. Streams [3:0] are used for [8] E12 J2. [7] C8 [6] C7 [5] D9 [4] E10 [3] B4 [2] F10 [ Zarlink Semiconductor Inc. Data Sheet Description TDM_D[15:0] ...

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... MHz, 8.192 MHz, 16.384 MHz [12] E13 depending on standard used. At [11] D12 8.192 Mbps only streams [3:0] are used. [10] A9 Streams [3:0] are used for J2. [9] C9 [8] B8 [7] D10 [6] B6 [5] F11 [4] E8 [3] A3 [2] C6 [ Zarlink Semiconductor Inc. Data Sheet Description ...

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... TDM port clock outputs. Will generate B6 1.544 MHz, 2.048 MHz, 4.096 MHz, F11 6.312 MHz, 8.192 MHz or 16.384 MHz E8 depending on standard used 8.192 Mbps only streams [1:0] are used. C6 Streams [1:0] are used for J2 Zarlink Semiconductor Inc. Data Sheet Description TDM_D[7:0] TDM_D[7:0] At 8.192 Mbps only ...

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... MHz, 2.048 MHz, 4.096 MHz, C4 6.312 MHz, 8.192 MHz or 16.384 MHz F9 depending on standard used. At 8.192 Mbps only streams [1:0] are used. Streams [1:0] are used for J2. 30 Zarlink Semiconductor Inc. Data Sheet Description TDM_D[3:0] At 8.192 Mbps TDM_D[3:0] At 8.192 Mbps only ...

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... Signal is normally active low, but can be active high depending on standard. Indicates the start of a TDM frame by pulsing every 125 µs. Normally will straddle rising edge or falling edge of clock pulse, depending on standard and clock frequency. 31 Zarlink Semiconductor Inc. Data Sheet Description TDM_FRAME TDM_F0 TDM_FRAME TDM_F0 ...

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... DPLL. Expected frequency range: 8 kHz - 16.384 MHz. Secondary reference output to optional external DPLL Multiplexed & frequency divided reference output for support of optional external DPLL. Expected frequency range: 8 kHz - 16.384 MHz. 32 Zarlink Semiconductor Inc. Data Sheet Description ...

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... All Packet Interface signals are 5 V tolerant, and all outputs are high impedance while System Reset is LOW. MII Mn_LINKUP_LED Mn_ACTIVE_LED - - Mn_RXCLK Table 8 - Packet Interface Signal Mapping - MII to GMII/TBI ZL50110/11/12/14 MII Port 2* MII Port 3 GMII Mn_LINKUP_LED Mn_ACTIVE_LED Mn_GIGABIT_LED Mn_GIGABIT_LED Mn_REFCLK Mn_RXCLK 33 Zarlink Semiconductor Inc. Data Sheet TBI (PCS) Mn_LINKUP_LED Mn_ACTIVE_LED Mn_REFCLK Mn_RBC0 ...

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... TXCLK and RXCLK. MII management data I/O. Common for all four MII ports 2.5 MHz bi-directional between the ZL50110/11/12/14 and the Ethernet station management entity. Data is passed synchronously with respect to M_MDC. 34 Zarlink Semiconductor Inc. Data Sheet TBI (PCS) Mn_RBC1 Mn_RXD[8] Mn_RXD[9] - Mn_TXD[8] ...

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... Used as a clock when in TBI mode. Accepts 62.5 MHz, and is 180° out of phase with M0_RBC0. each rising edge of M0_RBC1 and M0_RBC0, resulting in 125 MHz sample rate. 35 Zarlink Semiconductor Inc. Data Sheet Description MII 100 Mbps GMII 1 Gbps Receive data is clocked at ...

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... Accepts the following frequencies: 25.0 MHz [3] AA23 Transmit Data. Only half the bus (bits [3:0]) [2] W21 are used in MII mode. Clocked on rising [1] Y22 edge of M0_TXCLK (MII) or the rising edge [0] AA22 of M0_GTXCLK (GMII/TBI). 36 Zarlink Semiconductor Inc. Data Sheet Description MII 100 Mbps ...

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... When asserted (with M0_TXEN also asserted) the ZL50110/11/12/14 will transmit a non-valid symbol, somewhere in the transmitted frame. TBI - M0_TXD[9] Transmit Data. Clocked on rising edge of M0_GTXCLK. GMII/TBI only - Gigabit Transmit Clock Output of a clock for Gigabit operation at 125 MHz. 37 Zarlink Semiconductor Inc. Data Sheet Description ...

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... MHz sample rate. GMII/MII - M1_COL. Collision Detection. This signal is independent of M1_TXCLK and M1_RXCLK, and is asserted when a collision is detected on an attempted transmission active high, and only specified for half-duplex operation. 38 Zarlink Semiconductor Inc. Data Sheet Description MII 100 Mbps GMII 1 Gbps Receive data is clocked at ...

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... Transmit Enable. Asserted when the MAC has data to transmit, synchronously to M1_TXCLK with the first pre-amble of the packet to be sent. Remains asserted until the end of the packet transmission. Active high. TBI - M1_TXD[8] Transmit Data. Clocked on rising edge of M1_GTXCLK. 39 Zarlink Semiconductor Inc. Data Sheet Description MII 100 Mbps ...

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... AB21 Receive Data. Clocked on rising edge of [0] AD24 M2_RXCLK. Receive Data Valid. Active high. This signal is clocked on the rising edge of M2_RXCLK asserted when valid data is on the M2_RXD bus. 40 Zarlink Semiconductor Inc. Data Sheet Description Description MII 100 Mbps ...

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... LED drive for MAC 3 to indicate port is linked up. Logic 0 output = LED on Logic 1 output = LED off LED drive for MAC 3 to indicate port is transmitting or receiving packet data. Logic 0 output = LED on Logic 1 output = LED off 41 Zarlink Semiconductor Inc. Data Sheet Description MII 100 Mbps Description ...

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... Active high. Transmit Error. Transmitted synchronously with respect to M3_TXCLK, and active high. When asserted (with M3_TXEN also asserted) the ZL50111 will transmit a non-valid symbol, somewhere in the transmitted frame. 42 Zarlink Semiconductor Inc. Data Sheet Description MII 100 Mbps MII 100 Mbps ...

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... F5 AB4 [6] F4 AC3 [5] E3 AD2 [4] E4 AE1 [3] D1 AD1 [ [ [ [3] L5 Buffer memory parity. Synchronous to rising L2 [2] L6 edge of SYSTEM_CLK. Bit [7] is parity for L3 [1] K1 data byte [63:56], bit [0] is parity for data L4 [0] K2 byte [7:0]. 43 Zarlink Semiconductor Inc. Data Sheet Description ...

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... Synchronous Byte Write Enable G (Active Low). Must be asserted same clock cycle as RAM_ADDR. Enables RAM_DATA[55:48]. Synchronous Byte Write Enable H (Active Low). Must be asserted same clock cycle as RAM_ADDR. Enables RAM_DATA[63:56]. Read/Write Enable output Read = high Write = low 44 Zarlink Semiconductor Inc. Data Sheet Description ...

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... AB12 [2] AA11 [13] AE11 [12] AA12 AF14 AD14 45 Zarlink Semiconductor Inc. Data Sheet Description CPU Data Bus. Bi-directional data bus, synchronously transmitted with CPU_CLK rising edge. NOTE: as with all ports in the ZL50110/11/12/14 device, CPU_DATA[0] is the least significant bit (lsb). CPU Address Bus. Address input from ...

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... Only used for DMA transfers, not for normal register access. CPU PowerQUICC™ II Bus Interface clock input. 66 MHz clock, with minimum high/low time. Used to time all host interface signals into and out of ZL50110/11/12/14 device. 46 Zarlink Semiconductor Inc. Data Sheet Description ...

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... ZL50110/11/12/14 to indicate packet data is ready for transmission to the CPU, and request the host initiates a DMA read. Only used for DMA transfers, not for normal register access. CPU Interrupt 0 Request (Active Low) CPU Interrupt 1 Request (Active Low) 47 Zarlink Semiconductor Inc. Data Sheet Description ...

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... I Table 16 - System Function Interface Package Ball Definition ZL50110/11/12/14 Package Balls Zarlink Semiconductor Inc. Data Sheet Description System Clock Input. The system clock frequency is 100 MHz. The quality of SYSTEM_CLK, or the oscillator that drives SYSTEM_CLK directly impacts the adaptive clock recovery performance. See Section 6.3. ...

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... Recommend external pull-down. JTAG test mode select. Synchronous to JTAG_TCK rising edge. Used by the Test Access Port controller to set certain test modes. JTAG test data input. Synchronous to JTAG_TCK. JTAG test data output. Synchronous to JTAG_TCK. 49 Zarlink Semiconductor Inc. Data Sheet Description Description ...

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... R14 R15 R16 T11 T12 T13 T15 T16 T24 AA21 AB10 AF1 AF26 F12 F15 1.8 V VDD Power Supply for Core H6 H21 Region K21 M21 T21 V6 Y21 AA9 AA14 AA18 1.8 V PLL Power Supply 50 Zarlink Semiconductor Inc. Data Sheet Description Description ...

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... AUX2_CLKi[1] is connected to AUX2_CLKo[1] and AUX2_CLKi[0] is connected to AUX2_CLKo[0] through a zero ohm resistor. Auxiliary clock output. Typically AUX1_CLKo[1] is connected to AUX1_CLKi[1] and AUX1_CLKo[0] is connected to AUX1_CLKi[0] Auxiliary clock input. Typically AUX1_CLKi[1] is connected to AUX1_CLKo[1] and AUX1_CLKi[0] is connected to AUX1_CLKo[0] 51 Zarlink Semiconductor Inc. Data Sheet Description Description Description ...

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... Provider Edge Provider Edge Interworking Interworking Function Function OC-3, DS3 CESoP CESoP Metro Core Metropolitan Access Network (Resilient Packet Ring or Metro Ethernet) Metro Metro Access Access 52 Zarlink Semiconductor Inc. Data Sheet Customer Premises TDM f service ~ Extract Clock Campus T1/E1 Links ...

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... T1/E1 Broadband DLC Figure 8 - Digital Loop Carrier using CESoP ZL50110/11/12/14 GIGE Over N x GIGE Fiber Dedicated Central Fiber Links Office GIGE Over N x T1/E1 Fiber CESoP 53 Zarlink Semiconductor Inc. Data Sheet IP Edge Router or Multi-Service Switching Platform IP Central Office Switch (Class 5) PSTN ...

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... Mbps Concentrator T1/E1 Links Ethernet 10/100 Mbps Concentrator T1/E1 Links Figure 9 - Remote Concentrator using CESoP ZL50110/11/12/14 GIGE Over Fiber Remote Central Dedicated Office Fiber Links (Aggregation) GIGE Over Fiber Remote CESoP 54 Zarlink Semiconductor Inc. Data Sheet Nx GIGE IP STM1- 4 PSTN T1/E1 Links ...

Page 55

... Figure 10 - Cell Site Backhaul using CESoP ZL50110/11/12/14 ATM over T1/E1 Packet Switched Network ATM over T1/E1 CESoP CESoP GIGE over Fiber TDM over T1/E1 CESoP 55 Zarlink Semiconductor Inc. Data Sheet DS3/ 3G OC3 Radio Network Controller DS3/ 2.5G OC3 Base Station Controller DS3/ 2G OC3 ...

Page 56

... Equipment Architecture Example An equipment architecture example is shown in Figure 11, supporting T1/E1 ports is shown at the board level using Zarlink’s CESoP processors. In this example, the equipment consists of three line cards and an uplink card connected to a packet backplane. The first line card supports T1/E1 lines, containing up to 1024 DS0, for Nx64 kbps structured data transfer (SDT) CESoP connections ...

Page 57

... Manager TDM Protocol Packet Formatter Engine Receive Memory Management Unit On-chip RAM and SSRAM Interface Controller Off-chip Packet Memory 0-8 MBytes SSRAM 57 Zarlink Semiconductor Inc. Data Sheet TDM equipment constant bit rate TDM link Admin. Triple Packet Interface MAC JTAG Test ...

Page 58

... PKT to (TM (TM) to TDM TDM to (TM) to PKT PKT to (TM) to TDM TDM to (TM) to CPU TDM to (TM (TM) to CPU CPU to (TM) to TDM PKT to (TM) to CPU CPU to (TM) to PKT TDM to (TM) to TDM PKT to (TM) to PKT Table 24 - Standard Device Flows 58 Zarlink Semiconductor Inc. Data Sheet ...

Page 59

... Interface type Bit clock in and out Data in and out Bit clock out Frame pulse out Data in and out Bit clock in Frame in Data in and out 59 Zarlink Semiconductor Inc. Data Sheet Interfaces to Line interface unit Framers TDM backplane (master) Framers TDM backplane (slave) ...

Page 60

... Negative 2.048 244 Negative 4.096 244 Negative 16.384 244 Negative 2.048 488 Positive 8.192 122 Positive 60 Zarlink Semiconductor Inc. Data Sheet Frame Boundary Alignment Standard frame clock pulse Rising Straddles MSAN-126 Edge boundary Rev B (Issue 4) Falling Straddles Zarlink Edge ...

Page 61

... The Packet Transmit (PTX) circuit adds Layer 2 and Layer 3 protocol headers. The chosen protocol header combination for addition by the PTX must not exceed 64 bytes. The exception is context 127 (the 128th context), which must not exceed 56 bytes. ZL50110/11/12/14 PRS PRD DIV SRS SRD DIV 61 Zarlink Semiconductor Inc. Data Sheet PLL_PRI PLL_SE C CLOCK Internal DPLL FRAME ...

Page 62

... Channel x Channel 1 Channel 2 Channel x Static Padding (if required to meet minimum payload size) Ethernet FCS 62 Zarlink Semiconductor Inc. Data Sheet may include VLAN tagging e.g. IPv4, IPv6, MPLS e.g. UDP, L2TP, RTP, CESoPSN, SAToP TDM Payload (constructed by Payload Assembler) may also be placed in the ...

Page 63

... UDP, L2TP, RTP, (added by Packet Transmit) Upper layers (added by Protocol Engine) Octet 1 TDM Payload Octet 2 (constructed by Payload Assembler 1500 bytes Octet N Static Padding may also be placed in the (if required to meet minimum payload size) packet header Ethernet FCS 63 Zarlink Semiconductor Inc. Data Sheet CESoPSN, SAToP ...

Page 64

... Contexts in the Packet to TDM direction are placed in the UPDATE state when they are opened, pending first packet arrival packet never arrives the context will remain in the UDPATE state. ZL5011x Design Manual section “13.1 Understanding forceDelete” describes the procedure to close receive contexts in the UPDATE state. ZL50110/11/12/14 64 Zarlink Semiconductor Inc. Data Sheet ...

Page 65

... The disadvantage is the requirement for a common reference clock at each end of the packet network, which could either be the central office TDM clock, or provided by a global position system (GPS) receiver. ZL50110/11/12/14 at the customer premises must be exactly service 65 Zarlink Semiconductor Inc. Data Sheet ...

Page 66

... For applications where there is no common reference clock between provider edge units, an adaptive clock recovery technique is provided. The Adaptive clock recovery solution provided in the Zarlink CESoP products is a combination hardware and software. The chip contains a DCO per TDM port in unstructured mode, that enables the recovery independent clocks ...

Page 67

... The quality of the 100 MHz SYSTEM_CLK or the oscillator that drives SYSTEM_CLK directly impacts the adaptive clock recovery performance. Zarlink has a recommended oscillator and guidelines for the selection of an oscillator. Please refer to ZL5011x Design Manual section “3.6 System Clock Block” before choosing an oscillator. ...

Page 68

... DMA with external memory must use single packet mode. Refer to ZL5011x Design Manual for details. ZL50110/11/12/14 Packet Size >1000 bytes 60 bytes >1000 bytes 60 bytes 2 >1000 bytes 2 60 bytes Table 27 - DMA Maximum Bandwidths 68 Zarlink Semiconductor Inc. Data Sheet 1 Max Bandwidth Mbps 50 6 (29 each way) 11 (5.5 each way) ...

Page 69

... External Memory Requirements for different packet sizes 32 T1 streams, with Ethernet/MPLS/MPLS/RTP/CESoPSN headers 8192 7168 6144 5120 4096 3072 2048 1024 Figure 20 - External Memory Requirement for ZL50111 ZL50110/11/12/ 128 256 Jitter Buffer Size Zarlink Semiconductor Inc. Data Sheet 1 frame packets 8 frame packets 16 frame packets 1 T3 stream (1 frame) ...

Page 70

... This section outlines connection methods for the ZL50110/11/12/ Gigabit Ethernet environment recommended to ensure optimum performance. Two areas are covered: • Central Ethernet Switch • Redundant Ethernet Switch ZL50110/11/12/ 128 Jitter Buffer Size Zarlink Semiconductor Inc. Data Sheet 1 frame packets 8 frame packets 16 frame packets 256 ...

Page 71

... TDM data and control packets are directed to the appropriate ZL50110/11/12/14 device through the Ethernet Switch. There is no limit on the number of ZL50110/11/12/14 devices that can be connected in this configuration. ZL50110/11/12/14 Network Switch Ethernet GMII GMII GMII GMII ZL5011x ZL5011x TDM TDM 71 Zarlink Semiconductor Inc. Data Sheet GMII GMII ZL5011x TDM ...

Page 72

... Note that if JTAG Reset is not used it must be tied low. This is illustrated in the diagram shown in Figure 24. ZL50110/11/12/14 Network Network Ethernet Switch Ethernet Switch GMII GMII GMII GMII ZL5011x ZL5011x TDM TDM 72 Zarlink Semiconductor Inc. Data Sheet GMII GMII ZL5011x TDM ...

Page 73

... Debug option to freeze all internal state machines • JTAG (IEEE1149) Test Access Port • 3.3 V I/O Supply rail with 5 V tolerance • 1.8 V Core Supply rail • Fully compatible with the MT90880/1/2/3 Zarlink products ZL50110/11/12/14 I/O supply (3.3 V) Core supply (1.8 V) > 100 µ Zarlink Semiconductor Inc. ...

Page 74

... After the internal reset has been de-asserted the GPIO pins may be configured by the ADM module as either inputs or outputs. 7.11.4 System Tri-state Mode Selected by TEST_MODE[2:0] = 3'b011. All device output and I/O output drivers are tri-stated. ZL50110/11/12/14 System Test Mode test_mode[2:0] 3’b000 3’b011 Table 28 - Test Mode Control 74 Zarlink Semiconductor Inc. Data Sheet ...

Page 75

... PLL_SEC (Hex) (Note 16.384 1 1 2796 AEC 537 219 699 2BB 75 Zarlink Semiconductor Inc. Data Sheet Maximum Acceptable Input Wander tolerance (MHz) (UI) (Note 2) 0.008 ±1 1.544 ±1023 2.048 ±1023 4.096 ±1023 8.192 ±1023 ±1023 6.312 ±1023 0.008 ±1 (on 64k Hz) 0.064 ±1 (on 64 kHz) 0.064 ± ...

Page 76

... The time taken for n cycles must be within a programmed range, typically with n at 64, the time taken for consecutive cycles must be between 62 and 66 periods of the programmed frequency. The fail flags are independent of the preferred option for primary or secondary operation, will be asserted in the event of an invalid signal regardless of mode. ZL50110/11/12/14 76 Zarlink Semiconductor Inc. Data Sheet ...

Page 77

... Locking time is very difficult to determine because it is affected by many factors including: • initial input to output phase difference • initial input to output frequency difference • DPLL Loop Filter • DPLL Limiter (phase slope) ZL50110/11/12/14 77 Zarlink Semiconductor Inc. Data Sheet ...

Page 78

... There are 2 exceptions to this. a) When reference is 8 kHz, and reference frequency offset relative to the master is small, jitter master clock period is possible holdover mode huge amount of jitter had been present prior to entering holdover, then an additional 2 ns p-p is possible. ZL50110/11/12/ internal Tapped Delay Line (TDL). 78 Zarlink Semiconductor Inc. Data Sheet ...

Page 79

... Stratum 3, the DPLL will shift phase by no more than 20 ns per re-arrangement. Additionally the speed at which the change occurs is also critical. A large step change in output frequency is undesirable. The rate of change is programmable using the skew register maximum of 15 125 µs (124 ppm). ZL50110/11/12/14 Figure 25 - Jitter Transfer Function 79 Zarlink Semiconductor Inc. Data Sheet ...

Page 80

... Figure 26 - Jitter Transfer Function - Detail 9.0 Memory Map and Register Definitions All memory map and register definitions are included in the ZL50110/11/12/14 Programmers Model document. ZL50110/11/12/14 80 Zarlink Semiconductor Inc. Data Sheet ...

Page 81

... SS Symbol Min. Typ 3.0 3.3 DD_IO V 1.65 1.8 DD_CORE V 1.65 1.8 DD_PLL 2 2.0 - IH_5V 81 Zarlink Semiconductor Inc. Data Sheet Min. Max. Units -0.5 5.0 V -0.5 2.5 V -0.5 2 -0.5 7.0 V ± ± °C -55 +125 Test Max. Units Condition ° ...

Page 82

... DD_IO Symbol Min. Typ 2 1 1.2 T- Min. Typ. Max. 0 Zarlink Semiconductor Inc. Data Sheet Units. Test Condition µA No pull up/down V = 3.6 V DD_IO µA No pull up/down V = 3.6 V DD_IO pF pF µA Input µA Input µA Input at V DD_IO µA Input at V DD_IO ...

Page 83

... C4IH t 110 - 134 C4IL t FOIW 200 - 300 FOIS FOIH STOD STIS STIH 83 Zarlink Semiconductor Inc. Data Sheet Units Notes With respect to TDM_CLKi falling edge ns With respect to TDM_CLKi falling edge ns With respect to TDM_CLKi Load With respect to TDM_CLKi ns With respect to TDM_CLKi ...

Page 84

... STOD STOD Channel 127 bit 0 Channel 0 Bit 7 t C2IP t C4IP t FOIH t FOIS t FOIW t STIH t STIS t STOD Ch 31 Bit Bit 7 84 Zarlink Semiconductor Inc. Data Sheet Channel 0 bit 6 t STIH t STIS Ch0 bit7 t STOD Channel 0 bit 7 Channel 0 Bit 6 t STOD Ch 0 Bit 6 ...

Page 85

... STIS STIH Channel 0 Bit 7 t C16OP t FOD t FOD t STIH t STIS B7 t STOD Ch 0 Bit 7 85 Zarlink Semiconductor Inc. Data Sheet Max. Units Notes 68.0 ns 37.0 ns 37.0 ns 251.0 ns 129.0 ns 129 With respect to TDM_CLKo falling edge 5 ns With respect to TDM_CLKo falling edge 33 ...

Page 86

... DOD DOZ ZDO 102 - DIV t 90 122 Zarlink Semiconductor Inc. Data Sheet Channel 0 Bit 6 t STOD Ch 0 Bit 6 Max. Units Notes 122.074+Φ ns Note 1 Note 2 69+Φ ns 69+Φ Load - Load - 12 pF Note Load - 12 pF Note Note 4 112 ns Note 4 180 ns Note 5 ...

Page 87

... C4P t 110 - C4H t 110 - C4L t 60.9 61.0 C16P C16H C16L HZD 87 Zarlink Semiconductor Inc. Data Sheet Ts 0 Bit 2 t DOD Ts 0 Bit 2 Max. Units Notes 488.8 ns 268 ns 268 ns 244.4 ns 134 ns 134 ns 61 8.192 Mbps 100 ns At 2.048 Mbps 30 ns ...

Page 88

... C16H t C16P t t C16L HZD Ch 0 Bit 0 Symbol Min. Typ. t 22.353 CTP t 6.7 CTH t 6.7 CTL t 22.353 CRP t 9.0 CRH t 9.0 CRL Zarlink Semiconductor Inc. Data Sheet Max. Units Notes - 300 ns 150 ns 150 Bit Max. Units Notes ns DS3 clock DS3 clock ...

Page 89

... Table 35 - MII Transmit Timing - 100 Mbps ZL50110/11/12/14 t CTH t CTP CRH t CRP Symbol Min. Typ CPP CSP Table 34 - PAC Timing Specification 100 Mbps Symbol Min. Typ CHI CLO Zarlink Semiconductor Inc. Data Sheet t CTL t CRL Max. Units Notes - Units Notes Max Load = Load = 25 pF ...

Page 90

... Parameter Symbol TXCLK to TXER active delay (TXCLK rising edge) Table 35 - MII Transmit Timing - 100 Mbps TXCLK t EV TXEN t DV TXD[3:0] TXER Figure 34 - MII Transmit Timing Diagram ZL50110/11/12/14 100 Mbps Min. Typ Zarlink Semiconductor Inc. Data Sheet Units Notes Max Load = ...

Page 91

... RXER input hold time (RXCLK rising edge) Table 36 - MII Receive Timing - 100 Mbps RXCLK RXDV RXD[3:0] RXER ZL50110/11/12/14 100 Mbps Min. Typ DVS DVH ERS ERH DVS ERS Figure 35 - MII Receive Timing Diagram 91 Zarlink Semiconductor Inc. Data Sheet Units Notes Max CLO CHI t DVH ERH ...

Page 92

... Table 37 - GMII Transmit Timing - 1000 Mbps GTXCLK t EV TXEN t DV TXD[3:0] TXER ZL50110/11/12/14 1000 Mbps Min. Typ 2.5 - GCH t 2.5 - GCL GCR GCF t 1 Figure 36 - GMII Transmit Timing Diagram 92 Zarlink Semiconductor Inc. Data Sheet Units Notes Max. 8 Load = Load = Load = ...

Page 93

... Table 38 - GMII Receive Timing - 1000 Mbps RXCLK RXDV RXD[7:0] RXER ZL50110/11/12/14 1000 Mbps Min. Typ DVS DVH ERS ERH DVS ERS Figure 37 - GMII Receive Timing Diagram 93 Zarlink Semiconductor Inc. Data Sheet Units Notes Max. 8 CLO CHI t DVH ERH ...

Page 94

... Signal_Detect ZL50110/11/12/14 1000 Mbps Min. Typ Table 39 - TBI Timing - 1000 Mbps t DV Figure 38 - TBI Transmit Timing Diagram 94 Zarlink Semiconductor Inc. Data Sheet Units Notes Max. 8 2.4 Load = 10 pF Note 8 ...

Page 95

... Figure 39 - TBI Receive Timing Diagram Min. Typ. t 1990 2000 MP t 900 1000 MHI t 900 1000 MLO tMR - - MHI Zarlink Semiconductor Inc. Data Sheet /R/ /I/ Max. Units Notes 2010 ns Note 1 1100 ns 1100 Note Note 1 300 ns Note 2 t MLO ...

Page 96

... Phase 3 Phase 4 Phase 5 t RAV RAV t RBW BW2 BW3 BW4 BW5 t RDH t RDV t t RDS D(A1) Q(A2) Q(A3) t RPH t RPV t RPS P(A1) P(A2) P(A3) 96 Zarlink Semiconductor Inc. Data Sheet Max. Units Notes 4 ns Load Load Note Load Load Phase 6 Phase 7 Phase 8 ...

Page 97

... CEH t 4 CTS t 2 CTH t 2 CKS t 2 CKH t 2 CTV t 2 CWV t 2 CRV t 2 CDV t 3.2 SDV t 3.3 ODV t 3.2 OTV Table 42 - CPU Timing Specification 97 Zarlink Semiconductor Inc. Data Sheet Max. Units Notes Note 1 11.3 ns Note Note Note Note 1 10 ...

Page 98

... CAH t CES t CTH t CTS t t CDS t CTV t t OTV CTV Figure 44 - CPU Write - MPC8260 98 Zarlink Semiconductor Inc. Data Sheet 0 or more cycles 0 or more cycles t CSH t CEH t ODV t SDV t OTV more cycles t CSH t CEH CDH ...

Page 99

... CPU_CS and CPU_OE must BOTH be asserted to enable CWV t CKH t CKS t CSS t t CES CEH t CTH t CTS t CDH t CDS t CTV t t OTV CTV 99 Zarlink Semiconductor Inc. Data Sheet 0 or more cycles 0 or more cycles t CSH t CEH t ODV t SDV t OTV 0 or more cycles 0 or more cycles t CSH t OTV ...

Page 100

... The quality of SYSTEM_CLK, or the oscillator that drives SYSTEM_CLK directly impacts the adaptive clock recovery performance. See Section 6.3. ZL50110/11/12/14 Symbol Min. Typ. CLK - 100 FR CLK - - ACS CLK - - ACA Table 43 - System Clock Timing 100 Zarlink Semiconductor Inc. Data Sheet Max. Units Notes - MHz Note 1, Note 2 and Note 5 ±30 ppm Note 3 ±200 ppm Note 4 ...

Page 101

... Non Test (other than JTAG_TDO) signal output with respect to JTAG_CLK. ZL50110/11/12/14 Symbol Min. Typ 100 JCP LOW, t HIGH JRF RSTSU RST JSU JDV TPSU TPH TOPDV TPZ Table 44 - JTAG Interface Timing 101 Zarlink Semiconductor Inc. Data Sheet Max. Units Notes With respect to JTAG_CLK falling edge. Note Note Note Note Note ...

Page 102

... HIGH JTAG_TCK t TPH t TPSU JTAG_TMS Don't Care JTAG_TDI JTAG_TDO HiZ Figure 47 - JTAG Signal Timing JTAG_TCK t JTAG_TRST Figure 48 - JTAG Clock and Reset Timing ZL50110/11/12/14 t JCP t TPSU t TOPDV t t LOW HIGH t RST RSTSU 102 Zarlink Semiconductor Inc. Data Sheet t TPH DC t TPZ HiZ ...

Page 103

... ZL501x Power Consumption (Typical Conditions) 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0 Figure 49 - ZL50110/11/12/14 Power Consumption Plot ZL50110/11/12/ Number of Active Contexts 103 Zarlink Semiconductor Inc. Data Sheet 96 104 112 120 128 ...

Page 104

... In Summary: • Place series termination resistors as close to the pins as possible • Minimize output capacitance • Keep common interface traces close to the same length to avoid skew • Protect input clocks and signals from crosstalk ZL50110/11/12/14 104 Zarlink Semiconductor Inc. Data Sheet ...

Page 105

... The following external logic is required to implement the circuit: • 74LCX74 dual D-type flip-flop (one section of two) • 74LCX08 quad AND gate (one section of four) • 74LCX125 quad tri-state buffer (one section of four) • 4K7 resistor x2 ZL50110/11/12/14 105 Zarlink Semiconductor Inc. Data Sheet ...

Page 106

... The ZL50111/2 and ZL50110/4 have different Mx_LINKUP_LED pin assignments as shown in Table 46. Signal M0_LINKUP_LED M1_LINKUP_LED M2_LINKUP_LED M3_LINKUP_LED Table 45 - Mx_LINKUP_LED Pin Assignments ZL50110/11/12/14 +3V3 R1 4K7 Q D CPU_CS to ZL50110/11/14 Figure 50 - CPU_TA Board Circuit ZL50111/2 Pin AB23 F26 G23 G24 106 Zarlink Semiconductor Inc. Data Sheet + 3V3 R2 4K7 CPU_TA to CPU ZL50110/4 Pin G24 G23 NC NC ...

Page 107

... ZL50114 variants, resistors R1, R2, R3 and R5 as well as LEDs for M2 and M3 are not populated. M0_LINKUP_LED M1_LINKUP_LED ZL50110/1/4 M1/2_LINKUP_LED M0/3_LINKUP_LED Figure 51 - Mx_LINKUP_LED Stuffing Option ZL50110/11/12/14 R1 (AB23) R2 (F26) M2_LINKUP_LED R3 (G23) R4 M3_LINKUP_LED R5 (G24) R6 107 Zarlink Semiconductor Inc. Data Sheet VDD_IO M0_LINKUP_LED VDD_IO M1_LINKUP_LED VDD_IO VDD_IO ...

Page 108

... Table 46 lists the various components that are used for each variant. Component LED M1 LED M2 LED M3 LED Table 46 - Mx_LINKUP_LED Stuffing Option ZL50110/11/12/14 ZL50111/2 √ √ √ - √ - √ √ √ √ 108 Zarlink Semiconductor Inc. Data Sheet ZL50110 √ - √ √ √ ...

Page 109

... Telcordia GR-1244-CORE Stratum 3/4/4e • RFC4553; Structure-Agnostic TDM over Packet (SAToP) • ITU-T Y.1413 TDM-MPLS Network Interworking • Optional Packet Memory Device - Micron MT55L128L32P1 8 Mb ZBT-SRAM 14.2 Zarlink Standards • MSAN-126 Revision B, Issue 4; ST-BUS Generic Device Specification ZL50110/11/12/14 109 Zarlink Semiconductor Inc. Data Sheet ...

Page 110

... Application Program Interface ATM Asynchronous Transfer Mode CDP Context Descriptor Protocol (the protocol used by Zarlink’s MT9088x family of TDM-Packet devices) CESoP Circuit Emulation Services over Packet CESoPSN Circuit Emulation Services over Packet Switched Networks (draft-ietf-pwe3-cesopsn) CONTEXT A programmed connection of a number of TDM timeslots assembled into a unique packet stream. ...

Page 111

... Standard Telecom Bus, a standard interface for TDM data streams TDL Tapped Delay Line TDM Time Division Multiplexing UDP User Datagram Protocol (RFC 768) UI Unit Interval VLAN Virtual Local Area Network WFQ Weighted Fair Queuing ZBT Zero Bus Turnaround, a type of synchronous SRAM ZL50110/11/12/14 111 Zarlink Semiconductor Inc. Data Sheet ...

Page 112

... Zarlink Semiconductor 2003 All rights reserved ISSUE 213837 ACN DATE 12Dec02 19Aug03 APPRD. Package Code Previous package codes ...

Page 113

... Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned ...