ISP1105WTS STEricsson, ISP1105WTS Datasheet - Page 5

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ISP1105WTS

Manufacturer Part Number
ISP1105WTS
Description
Manufacturer
STEricsson
Datasheet

Specifications of ISP1105WTS

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Table 3.
ISP1105_1106_10
Product data sheet
Symbol
OE
RCV
VP
VM
SUSPND
MODE
GND
V
SPEED
D−
D+
CC(I/O)
[1]
Pin description
Pin
ISP1105
BSTM WTS,
pad
die
10
6.2 Pin description
1
2
3
4
5
6
7
8
9
WTM
pad
die
10
1
2
3
4
5
6
7
8
9
ISP1106
DHTM WTS
10
12
11
4
5
6
3
7
8
9
-
10
1
2
3
4
5
6
7
8
9
-
Type Description
I
O
O
O
I
I
-
-
I
AI/O negative USB data bus connection (analog, differential); for low-speed
AI/O positive USB data bus connection (analog, differential); for full-speed
Rev. 10 — 28 September 2009
output enable input (CMOS level with respect to V
enables the transceiver to transmit data on the USB bus
input pad; push pull; CMOS
differential data receiver output (CMOS level with respect to V
driven LOW when input SUSPND is HIGH; the output state of RCV is
preserved and stable during an SE0 condition
output pad; push pull; 4 mA output drive; CMOS
single-ended D+ receiver output (CMOS level with respect to V
for external detection of single-ended zero (SE0), error conditions,
speed of connected device; driven HIGH when no supply voltage is
connected to V
output pad; push pull; 4 mA output drive; CMOS
single-ended D− receiver output (CMOS level with respect to V
for external detection of single-ended zero (SE0), error conditions,
speed of connected device; driven HIGH when no supply voltage is
connected to V
output pad; push pull; 4 mA output drive; CMOS
suspend input (CMOS level with respect to V
enables low-power state while the USB bus is inactive and drives
output RCV to a LOW level
input pad; push pull; CMOS
mode input (CMOS level with respect to V
enables the differential input mode (VPO, VMO) whereas a LOW level
enables a single-ended input mode (VO, FSE0); see
Table 6
input pad; push pull; CMOS
ground supply
supply voltage for digital I/O pins (1.65 V to 3.6 V). When V
not connected, the (D+, D−) pins are in three-state; this supply pin is
totally independent of V
V
speed selection input (CMOS level with respect to V
the slew rate of differential data outputs D+ and D− according to the
transmission speed
LOW — low-speed (1.5 Mbit/s)
HIGH — full-speed (12 Mbit/s)
input pad; push pull; CMOS
mode connect to pin V
mode connect to pin V
reg(3.3)
voltage
[2]
CC(5.0)
CC(5.0)
and V
and V
pu(3.3)
pu(3.3)
CC(5.0)
reg(3.3)
reg(3.3)
via a 1.5 kΩ resistor
via a 1.5 kΩ resistor
and V
reg(3.3)
Advanced USB transceivers
ISP1105/1106
CC(I/O)
and must never exceed the
CC(I/O)
© ST-ERICSSON 2009. All rights reserved.
); a HIGH level
CC(I/O)
); a HIGH level
CC(I/O)
Table 5
, active LOW);
); adjusts
CC(I/O)
and
CC(I/O)
CC(I/O)
CC(I/O)
5 of 25
is
);
);
);

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