NUC140LD2CN Nuvoton Technology Corporation of America, NUC140LD2CN Datasheet - Page 173

• Manufacturer Part Number: NUC140LD2CN
• Description: IC MCU 32BIT 64KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC140LD2CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Extra Configuration Register (USB_CFGPx) x = 0~5
Register
USB_CFGP0
USB_CFGP1
USB_CFGP2
USB_CFGP3
USB_CFGP4
USB_CFGP5
Bits
[31:2]
[1]
[0]
31
23
15
7
NuMicro™ NUC130/NUC140 Technical Reference Manual
Offset
USB_BA+0x02C R/W
USB_BA+0x03C R/W
USB_BA+0x04C R/W
USB_BA+0x05C R/W
USB_BA+0x06C R/W
USB_BA+0x07C R/W
Descriptions
Reserved
SSTALL
CLRRDY
30
22
14
6
R/W
Reserved
Set STALL
1 = Set the device to respond STALL automatically
0 = Disable the device to response STALL
Clear Ready
When the MXPLD register is set by user, it means that the endpoint is ready to
transmit or receive data. If the user wants to turn off this transaction before the
transaction start, users can set this bit to 1 to turn it off and it is auto clear to 0.
For IN token, write ‘1’ is used to clear the IN token had ready to transmit the data to
USB.
For OUT token, write ‘1’ is used to clear the OUT token had ready to receive the data
from USB.
This bit is write 1 only and it is always 0 when it was read back.
29
21
13
5
Reserved
Description
Endpoint 0 Set Stall and Clear In/Out Ready Control Register 0x0000_0000
Endpoint 1 Set Stall and Clear In/Out Ready Control Register 0x0000_0000
Endpoint 2 Set Stall and Clear In/Out Ready Control Register 0x0000_0000
Endpoint 3 Set Stall and Clear In/Out Ready Control Register 0x0000_0000
Endpoint 4 Set Stall and Clear In/Out Ready Control Register 0x0000_0000
Endpoint 5 Set Stall and Clear In/Out Ready Control Register 0x0000_0000
28
20
12
4
- 173 -
Reserved
Reserved
Reserved
27
19
11
3
Publication Release Date: June 14, 2011
26
18
10
2
SSTALL
25
17
9
1
Revision V2.01
Reset Value
CLRRDY
24
16
8
0