NUC140LD2CN Nuvoton Technology Corporation of America, NUC140LD2CN Datasheet - Page 461

• Manufacturer Part Number: NUC140LD2CN
• Description: IC MCU 32BIT 64KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC140LD2CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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NuMicro™ NUC130/NUC140 Technical Reference Manual
TXBUSY
TXEMPTY
TXFULL
TXTHF
TXOVF
TXUDF
Reserved
RXEMPTY
Transmit Busy
This bit is clear to 0 when all data in transmit FIFO and shift buffer is shifted out. And
set to 1 when 1st data is load to shift buffer.
1 = Transmit shift buffer is busy
0 = Transmit shift buffer is empty
This bit is read only.
Transmit FIFO empty
This bit reflect data word number in transmit FIFO is zero
1 = Empty
0 = Not empty
This bit is read only.
Transmit FIFO full
This bit reflect data word number in transmit FIFO is 8
1 = Full.
0 = Not full.
This bit is read only
Transmit FIFO threshold flag
When data word(s) in transmit FIFO is equal or lower than threshold value set in
TXTH[2:0] the TXTHF bit becomes to 1. It keeps at 1 till TXFIFO_LEVEL[3:0] is higher
than TXTH[1:0] after software write TXFIFO register.
1 = Data word(s) in FIFO is equal or lower than threshold level
0 = Data word(s) in FIFO is higher than threshold level
This bit is read only
Transmit FIFO overflow flag
Write data to transmit FIFO when it is full and this bit set to 1
1 = Overflow
0 = No overflow
Software can write 1 to clear this bit to zero
Transmit FIFO underflow flag
When transmit FIFO is empty and shift logic hardware read data from data FIFO
causes this set to 1.
1 = Underflow
0 = No underflow
Software can write 1 to clear this bit to zero
Reserved
Receive FIFO empty
This bit reflects data words number in receive FIFO is zero
1 = Empty
0 = Not empty
This bit is read only.
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Publication Release Date: June 14, 2011
Revision V2.01