NUC140LD2CN Nuvoton Technology Corporation of America, NUC140LD2CN Datasheet - Page 8

• Manufacturer Part Number: NUC140LD2CN
• Description: IC MCU 32BIT 64KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC140LD2CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 5-26: I
Figure 5-27 Legend for the following five figures ......................................................................... 213
Figure 5-28 Master Transmitter Mode ......................................................................................... 214
Figure 5-29 Master Receiver Mode.............................................................................................. 215
Figure 5-30 Slave Transmitter Mode............................................................................................ 216
Figure 5-31 Slave Receiver Mode................................................................................................ 217
Figure 5-32 GC Mode .................................................................................................................. 218
Figure 5-33 PWM Generator 0 Clock Source Control.................................................................. 221
Figure 5-34 PWM Generator 0 Architecture Diagram.................................................................. 221
Figure 5-35 PWM Generator 2 Clock Source Control.................................................................. 222
Figure 5-36 PWM Generator 2 Architecture Diagram.................................................................. 222
Figure 5-37 PWM Generator 4 Clock Source Control.................................................................. 223
Figure 5-38 PWM Generator 4 Architecture Diagram.................................................................. 223
Figure 5-39 PWM Generator 6 Clock Source Control.................................................................. 224
Figure 5-40 PWM Generator 6 Architecture Diagram.................................................................. 224
Figure 5-41 Legend of Internal Comparator Output of PWM-Timer ............................................ 225
Figure 5-42 PWM-Timer Operation Timing.................................................................................. 226
Figure 5-43 PWM Double Buffering Illustration............................................................................ 226
Figure 5-44 PWM Controller Output Duty Ratio........................................................................... 227
Figure 5-45 Paired-PWM Output with Dead Zone Generation Operation ................................... 227
Figure 5-46 Capture Operation Timing ........................................................................................ 228
Figure 5-47 PWM Group A PWM-Timer Interrupt Architecture Diagram..................................... 229
Figure 5-48 PWM Group B PWM-Timer Interrupt Architecture Diagram..................................... 229
Figure 5-49 RTC Block Diagram .................................................................................................. 258
Figure 5-50 SPI Block Diagram.................................................................................................... 277
Figure 5-51 SPI Master Mode Application Block Diagram........................................................... 278
Figure 5-52 SPI Slave Mode Application Block Diagram............................................................. 278
Figure 5-53 Variable Serial Clock Frequency .............................................................................. 280
Figure 5-54 32-Bit in one Transaction.......................................................................................... 280
Figure 5-55 Two Transactions in One Transfer (Burst Mode) ..................................................... 281
Figure 5-56 Byte Reorder............................................................................................................. 282
Figure 5-57 Timing Waveform for Byte Suspend......................................................................... 283
Figure 5-58 Two Bits Transfer Mode (slave mode)...................................................................... 284
Figure 5-59 FIFO mode Block Diagram ....................................................................................... 285
Figure 5-60 SPI Timing in Master Mode ...................................................................................... 287
Figure 5-61 SPI Timing in Master Mode (Alternate Phase of SPICLK) ....................................... 288
NuMicro™ NUC130/NUC140 Technical Reference Manual
2
C Time-out Count Block Diagram ......................................................................... 202
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Publication Release Date: June 14, 2011
Revision V2.01