NAND512R3A2SZA6E Micron Technology Inc, NAND512R3A2SZA6E Datasheet
NAND512R3A2SZA6E
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NAND512R3A2SZA6E Summary of contents
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... Mbit, 528 Byte/264 Word page, x8/x16, 1.8 V/3 V Features Density – 512 Mbit: 4096 blocks NAND Flash interface – x16 bus width – Multiplexed address/data Memory configuration – Page size: x8 device: (512 + 16 spare) Bytes x16 device: (256 + 8 spare) Words – Block size: ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Numonyx SLC Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.1 Bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.2 NAND Flash memory failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.3 Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.4 Wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.5 Error correction code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.6 Hardware simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.6.1 7.6.2 8 Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 32 9 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters ...
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... Table 10. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 11. Copy back program addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 12. Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 13. Electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 14. NAND Flash failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 15. Program, erase times and program erase endurance cycles . . . . . . . . . . . . . . . . . . . . . . . 32 Table 16. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 17. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 18. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 19. ...
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Numonyx SLC List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint. To extend the lifetime of NAND Flash devices it is strongly recommended to implement an error correction code (ECC). The use of ECC correction allows to achieve up to 100,000 program/erase cycles for each block ...
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... Bytes 2.7 to 3.6 V 8K+256 Words 32 pages x 4096 blocks 16K+512 Bytes 1.7 to 1.95 V 8K+256 Words I/O8-I/O15, x16 E I/O0-I/O7, x8/x16 R W NAND flash 210403 - Rev 3 Description Timings Random Sequential Page Block access access program erase Max Min Typ Typ 12 µ 200 µ ...
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... Function memory array P/E/R controller, high voltage generator Page buffer Y decoder I/O buffers & latches RB I/O0-I/O7, x8/x16 I/O8-I/O15, x16 210403 - Rev 3 Numonyx SLC Direction I/O I/O Input Input Input Input Output Input Input Power supply Ground – – NAND flash AI07561c ...
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... Numonyx SLC Figure 3. TSOP48 connections - x8 devices NAND flash (x8 210403 - Rev 3 Description I/O7 I/O6 I/O5 I/ I/O3 I/O2 I/O1 I/ AI07585C 9/51 ...
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Description Figure 4. VFBGA63 connections - x8 devices (top view through package 10/ ...
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... Word spare area. Refer to Bad blocks The NAND Flash 528 Byte/264 Word page devices may contain bad blocks, that is blocks that contain one or more invalid bits whose reliability is not guaranteed. Additional bad blocks may develop during the lifetime of the device. ...
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Memory array organization Figure 5. Memory array organization x8 DEVICES Block = 32 pages Page = 528 bytes (512+16) 1st half page 2nd half page (256 bytes) (256 bytes) Block Page 512 Bytes Page buffer, 512 bytes 512 bytes 12/51 ...
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Numonyx SLC Signal descriptions See Figure 1: Logic connected to the devices. Table 5. Signal descriptions Symbol Input/Output signals I/O0-I/O7 I/O8-I/O15 Control signals diagram, and Table 3: Signal Table 5 provides the detailed ...
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Signal descriptions Table 5. Signal descriptions (continued) Symbol Supply 14/51 Type The Read Enable, R, controls the sequential data output during read operations. Data is valid t Input edge of R. The ...
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Numonyx SLC Bus operations There are six standard bus operations that control the memory. Each of these is described in this section, see 4.1 Command input Command input bus operations are used to give commands to ...
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Bus operations 4.5 Write protect Write protect bus operations are used to protect the memory against program or erase operations. When the Write Protect signal is Low the device will not accept program or erase operations and so the contents ...
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Numonyx SLC Table 9. Address definition Address A25 A9 - A13 A14 - A25 A8 210403 - Rev 3 Bus operations Definition Column address Page address Address in block Block address A8 ...
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Command set 5 Command set All bus write operations to the device are interpreted by the command interface. The commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when the Command Latch Enable signal ...
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... Device operations 6.1 Pointer operations As the NAND Flash memories contain two different areas for x16 devices and three different areas for x8 devices (see act as pointers to the different areas of the memory array (they select the most significant column address). The Read A and Read B commands act as pointers to the main memory area. Their use depends on the bus width of the device ...
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Device operations Figure 7. Pointer operations for programming Address 80h I/O 00h Inputs Areas can be programmed depending on how much data is input. Subsequent 00h commands can be omitted. Address 80h I/O 01h Inputs Areas B, ...
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Numonyx SLC 6.2.2 Page read After the random read access the page data is transferred to the page buffer in a time of t (refer to Table 22 WHBH goes High. The data can then be read ...
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Device operations Figure 9. Sequential row read operations (Read Busy time) RB 00h/ I/O Address Inputs 01h/ 50h Command Code Figure 10. Sequential row read block diagrams Read A Command, x8 Devices Area B Area A (1st half Page) (2nd ...
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Numonyx SLC 6.3 Page program The page program operation is the standard operation to program data to the memory array. The main area of the memory array is programmed by page, however partial page programming is allowed ...
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Device operations 6.4 Copy back program The copy back program operation is used to copy the data stored in one page and reprogram it in another page. The copy back program operation does not require external memory and so the ...
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Numonyx SLC 6.5 Block erase Erase operations are done one block at a time. An erase operation sets all of the bits in the addressed block to ‘1’. All previous data in the block is lost. An ...
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Device operations 6.7 Read status register The device contains a status register which provides information on the current or previous program or erase operation. The various bits in the status register convey information and errors on the operation. The status ...
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Numonyx SLC Table 12. Status register bits Bit SR0 6.8 Read electronic signature The device contains a manufacturer code and device code. To read these codes two steps are required: 1. first use one bus write cycle ...
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... This section gives information on the software algorithms that Numonyx recommends to implement to manage the bad blocks and extend the lifetime of the NAND device. NAND Flash memories are programmed and erased by Fowler-Nordheim tunneling using a high voltage. Exposing the device to a high voltage for extended periods can cause the oxide layer to be damaged ...
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... Numonyx SLC Refer to Table 14 Table 14. NAND Flash failure modes Operation Erase Program Read Figure 15. Bad block management flowchart for the procedure to follow if an error occurs during an operation. START Block Address = Block 0 Data NO Bad Block table = FFh? YES Last NO block? YES END ...
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... Error correction code Users must implement an error correction code (ECC) to identify and correct errors in the data stored in the NAND Flash memories. The ECC implemented must be able to correct 1 bit every 512 Bytes. Sensible data stored in the spare area must be covered by ECC as well. ...
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... Behavioral simulation models Denali software corporation models are platform independent functional models designed to assist customers in performing entire system simulations (typical VHDL/Verilog). These models describe the logic behavior and timings of NAND Flash devices, and so allow software to be developed before hardware. 7.6.2 IBIS simulations models IBIS (I/O buffer information specification) models describe the behavior of the I/O buffers and electrical characteristics of Flash devices ...
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... V for less than 20 ns during transitions on I/O pins. DD 32/51 Min 100,000 10 Table 16: Absolute maximum Parameter 1.8 V devices 3 V devices 1.8 V devices 3 V devices 210403 - Rev 3 Numonyx SLC NAND Flash Unit Typ Max 200 500 µ cycles years ratings, may Value ...
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... TTL GATE devices 1.8 V devices 3 V devices 1.8 V devices 3 V devices ref (1)(2) Parameter Test conditions and C are not 100% tested. IN I/O 210403 - Rev 3 DC and AC parameters NAND Flash Units Min Max 1.7 1.95 V 2.7 3.6 –40 85 ° 0.4 2.4 0 ...
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... DC and AC parameters M Figure 17. Equivalent testing circuit for AC characteristics measurement NAND flash Table 19. DC characteristics, 1.8 V devices Symbol Parameter I DD1 Operating current I DD2 I DD3 I Standby current (TTL) DD4 I Standby current (CMOS) DD5 I Input leakage current LI I Output leakage current LO V Input high voltage ...
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Numonyx SLC Table 20. DC characteristics devices Symbol Parameter I DD1 Operating current I DD2 I DD3 I Standby current (TTL) DD4 I Standby current (CMOS) DD5 I Input leakage current LI I Output leakage ...
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DC and AC parameters Table 22. AC characteristics for operations Alt. Symbol symbol t Address Latch Low to ALLRL1 t AR Read Enable Low t ALLRL2 t t Ready/Busy High to Read Enable Low BHRL RR t BLBH1 t t ...
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Numonyx SLC Figure 18. Command Latch AC waveforms CL tCLHWH (CL Setup time) tELWH H(E Setup time tALLWH (ALSetup time) AL I/O Figure 19. Address Latch AC waveforms CL tELWH (E Setup time) E tWLWH ...
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DC and AC parameters Figure 20. Data Input Latch AC waveforms CL E tALLWH (ALSetup time) AL tWLWH W (Data Setup time) I/O Figure 21. Sequential data output after read AC waveforms Low Low, W ...
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Numonyx SLC Figure 22. Read status register AC waveforms tCLHWH tELWH Figure 23. Read electronic signature AC waveforms I/O 90h Read Electronic Signature Command 1. Refer to Table 13 for the values ...
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DC and AC parameters Figure 24. Page read A/read B operation AC waveforms CL E tWLWL 00h or Add.N I/O 01h cycle 1 Command Code 40/51 tWHBL tALLRL2 tWHBH tRLRH tBLBH1 Data Add.N Add.N Add.N cycle ...
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Numonyx SLC Figure 25. Read C operation, one page AC waveforms Add. M I/O 50h cycle 1 RB Command Code 1. A0-A7 is the address in the spare memory area, where A0-A3 ...
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DC and AC parameters Figure 26. Page program AC waveforms CL E tWLWL (Write Cycle time Add.N I/O 80h cycle 1 RB Page Program Setup Code 42/51 tWLWL tWHBL Add.N Add.N Add.N N cycle 4 cycle 2 ...
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Numonyx SLC Figure 27. Block erase AC waveforms CL E tWLWL (Write Cycle time Add. I/O 60h cycle 1 RB Block Erase Block Address Input Setup Command Figure 28. Reset AC waveforms W AL ...
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DC and AC parameters Figure 29. Program/erase enable waveforms W tVHWH WP RB I/O Figure 30. Program/erase disable waveforms W tVLWH WP High RB I/O 10.1 Ready/Busy signal electrical characteristics Figure 31, Figure 32 signal. The value required for the ...
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Numonyx SLC Figure 31. Ready/Busy AC waveform Figure 32. Ready/Busy load circuit 1.8 V device - 0 0.1 V 3.3 V device - 0.4 ...
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DC and AC parameters Figure 33. Resistor value versus waveform timings for Ready/Busy signal 25°C. 10.2 Data protection The Numonyx NAND device is designed to guarantee data protection during power transitions detection circuit disables all ...
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Numonyx SLC Package mechanical To meet environmental requirements, Numonyx offers these devices in RoHS compliant packages, which have a lead-free second-level interconnect. The category of second-level interconnect is marked on the package and on the inner ...
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Package mechanical Figure 36. VFBGA63 1. +15, 0.8 mm pitch, package outline FD1 BALL "A1" 1. Drawing is not to scale. Table 24. VFBGA63 ...
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... Numonyx SLC Ordering information Table 25. Ordering information scheme Example: Device type NAND = NAND Flash memory Density 512 = 512 Mbit Operating voltage 1 2 Bus width x16 Family identifier A = 528 Byte/264 Word page Device options option (Chip Enable ‘care’; sequential row read enabled Chip Enable don’ ...
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Revision history 13 Revision history Table 26. Document revision history Date 03-Feb-2010 29-Jul-2010 25-Mar-2011 50/51 Revision 1 Initial release. 2 Added information about 1.8 V devices. 3 Removed “Preliminary Data” status from document. 210403 - Rev 3 Numonyx SLC SP ...
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... Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. ...