AGLN250V2-ZCSG81 Actel, AGLN250V2-ZCSG81 Datasheet - Page 26

• Manufacturer Part Number: AGLN250V2-ZCSG81
• Manufacturer: Actel

IGLOO nano DC and Switching Characteristics
2 -1 2
Power Calculation Methodology
This section describes a simplified method to estimate power consumption of an application. For
more accurate and detailed power estimations, use the SmartPower tool in Actel Libero IDE
software.
The power calculation methodology described below uses the following variables:
Methodology
Total Power Consumption—P
Total Static Power Consumption—P
Total Dynamic Power Consumption—P
Global Clock Contribution—P
Sequential Cells Contribution—P
•
•
•
•
•
•
•
•
P
P
P
P
P
TOTAL
STAT
DYN
CLOCK
S-CELL
The number of PLLs as well as the number and the frequency of each output clock
generated
The number of combinatorial and sequential cells used in the design
The internal clock frequencies
The number and the standard of I/O pins used in the design
The number of RAM blocks used in the design
Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in
page
Enable rates of output buffers—guidelines are provided for typical applications in
Table 2-19 on page
Read rate and write rate to the memory—guidelines are provided for typical applications in
Table 2-19 on page
in the design.
= P
P
P
= (P
N
N
in
N
Table 2-18 on page
F
N
P
N
multi-tile sequential cell is used, it should be accounted for as 1.
α
page
F
CLK
CLK
= P
STAT
DYN
AC1
= N
BANKS
SPINE
ROW
S-CELL
S-CELL
= (P
1
Table 2-18 on page
CLOCK
DC1
is the toggle rate of VersaTile outputs—guidelines are provided in
2-14.
STAT
, P
S-CELL
is the global clock signal frequency.
is the global clock signal frequency.
AC1
is the total dynamic power consumption.
is the total static power consumption.
2-14.
is the number of VersaTile rows used in the design—guidelines are provided in
is the number of global spines used in the user design—guidelines are provided
AC2
or P
is the number of VersaTiles used as sequential modules in the design.
is the number of VersaTiles used as sequential modules in the design. When a
is the number of I/O banks powered in the design.
+ P
+ P
+ N
* (P
, P
DC2
DYN
S-CELL
SPINE
AC3
AC5
or P
, and P
*P
+ P
+
2-14.
2-14. The calculation should be repeated for each clock domain defined
DC3
AC2
α
C-CELL
2-14.
1
) + N
+ N
/ 2 * P
2-14.
AC4
CLOCK
TOTAL
ROW
BANKS
+ P
are device-dependent.
A d v a n c e v 0. 3
S-CELL
AC6
NET
*P
STAT
) * F
* P
AC3
+ P
DC5
DYN
INPUTS
+ N
CLK
S-CELL
+ P
* P
OUTPUTS
AC4
) * F
+ P
CLK
MEMORY
+ P
PLL
Table 2-18 on
Table 2-18 on