AGLN250V2-ZCSG81 Actel, AGLN250V2-ZCSG81 Datasheet - Page 81

• Manufacturer Part Number: AGLN250V2-ZCSG81
• Manufacturer: Actel

Table 2-93 • IGLOO nano CCC/PLL Specification
Parameter
Clock Conditioning Circuitry Input Frequency f
Clock Conditioning Circuitry Output Frequency f
Delay Increments in Programmable Delay Blocks
Number of Programmable Values in Each Programmable Delay Block
Serial Clock (SCLK) for Dynamic PLL
Input Cycle-to-Cycle Jitter (peak magnitude)
CCC Output Peak-to-Peak Period Jitter F
Acquisition Time
Tracking Jitter
Output Duty Cycle
Delay Range in Block: Programmable Delay 1
Delay Range in Block: Programmable Delay 2
Delay Range in Block: Fixed Delay
Notes:
1. This delay is a function of voltage and temperature. See
2. T
3. The AGLN010, AGLN015, and AGLN020 devices do not support PLLs.
4. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input
5. Maximum value obtained for a STD speed grade device in Worst-Case Commercial conditions. For specific
for deratings.
clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by period
jitter parameter.
junction temperature and voltage supply levels, refer to
for derating values.
0.75 MHz to 24 MHz
24 MHz to 100 MHz
100 MHz to 160 MHz
J
= 25°C, V
For IGLOO nano V2 Devices, 1.2 V DC Core Supply Voltage
CC
= 1.2 V
1, 2
5
CCC_OUT
1, 2
1, 2,
IN_CCC
OUT_CCC
A dv a n c e v 0. 3
1, 2
LockControl = 0
LockControl = 1
LockControl = 0
LockControl = 1
Table 2-6 on page 2-6
Table 2-6 on page 2-6
IGLOO nano DC and Switching Characteristics
Network
1 Global
0.50%
1.00%
2.50%
0.025
Used
Min.
0.75
48.5
2.3
1.5
Max Peak-to-Peak Period Jitter
External
FB Used
0.75%
1.50%
3.75%
Typ.
and
580
and
5.7
Table 2-7 on page 2-7
Table 2-7 on page 2-7
Networks
3 Global
0.70%
1.20%
2.75%
20.86
20.86
Max.
Used
0.25
160
160
300
51.5
6.0
60
32
4
3
Units
MHz
MHz
MHz
ms
ns
µs
ns
ns
%
ps
ns
ns
ns
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