ADNS-4000 Avago Technologies US Inc., ADNS-4000 Datasheet - Page 9

• Manufacturer Part Number: ADNS-4000
• Description: SENSOR OPTICAL MOUSE LP 8DIP
• Manufacturer: Avago Technologies US Inc.

Specifications of ADNS-4000

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 3. AC Electrical Specifi cations
Electrical characteristics over recommended operating conditions. Typical values at 25 °C, VDD = 2.8 V.
9
Parameter
Motion Delay after
Reset
Forced Rest Enable
Wake from Forced
Rest
Power Down
Wake from Power
Down
MISO Rise Time
MISO Fall Time
MISO Delay after
SCLK
MISO Hold Time
MOSI Hold Time
MOSI Setup Time
SPI Time between
Write Commands
SPI Time between
Write and Read Com-
mands
SPI Time between
Read and Subsequent
Commands
SPI Read Address-Data
Delay
NCS Inactive after Mo-
tion Burst
NCS to SCLK Active
SCLK to NCS Inactive
(for Read Operation)
SCLK to NCS Inactive
(for Write Operation)
NCS to MISO high-Z
Transient Supply
Current
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
I
DDT
MOT-RST
REST-EN
REST-DIS
PD
WAKEUP
r-MISO
f-MISO
DLY-MISO
hold-MISO
hold-MOSI
setup-MOSI
SWW
SWR
SRW
SRR
SRAD
BEXIT
NCS-SCLK
SCLK-NCS
SCLK-NCS
NCS-MISO
Min.
50
500
200
120
30
20
250
4
250
120
120
20
Typ.
40
40
Max.
50
1
1
50
55
200
200
120
1/f
250
60
SCLK
Units
ms
s
s
ms
ms
ns
ns
ns
ns
ns
ns
μs
μs
ns
μs
ns
ns
ns
μs
ns
mA
Notes
From RESET register write to valid motion
From Rest Mode(RM) bits set to target rest
mode
From Rest Mode(RM) bits cleared to valid
motion
From PD active (when bit 1 of register 0x0d is
set) to low current
From PD inactive (when write 0x5a to regis-
ter 0x3a) to valid motion
C
C
From SCLK falling edge to MISO data valid,
no load conditions
Data held until next falling SCLK edge
Amount of time data is valid after SCLK rising
edge
From data valid to SCLK rising edge
From rising SCLK for last bit of the fi rst data
byte, Commands to rising SCLK for last bit of
the second data byte
From rising SCLK f or last bit of the fi rst data
byte, to rising SCLK for last bit of the second
address byte
From rising SCLK for last bit of the fi rst data
byte, to falling SCLK for the fi rst bit of the
next address
From rising SCLK for last bit of the address
byte, to falling SCLK for fi rst bit of data being
read
Minimum NCS inactive time after motion
burst before next SPI usage
From NCS falling edge to fi rst SCLK falling
edge
From last SCLK rising edge to NCS rising
edge, for valid MISO data transfer
From last SCLK rising edge to NCS rising
edge, for valid MOSI data transfer
From NCS rising edge to MISO high-Z state
Max supply current during a VDD ramp from
0 to VDD
L
L
= 100 pF
= 100 pF