C8051T601-GMR Silicon Laboratories Inc, C8051T601-GMR Datasheet - Page 164

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C8051T601-GMR

Manufacturer Part Number
C8051T601-GMR
Description
MCU 8-Bit C8051T60x 8051 CISC 8KB EPROM 1.8V/3V 14-Pin QFN EP T/R
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of C8051T601-GMR

Package
14QFN EP
Device Core
8051
Family Name
C8051T60x
Maximum Speed
25 MHz
Ram Size
256 Byte
Program Memory Size
8 KB
Operating Supply Voltage
1.8|3 V
Data Bus Width
8 Bit
Program Memory Type
EPROM
Number Of Programmable I/os
8
Interface Type
I2C/SMBus/UART
Operating Temperature
-40 to 85 °C
Number Of Timers
3
C8051T600/1/2/3/4/5/6
26.3.1. Edge-triggered Capture Mode
In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA coun-
ter/timer and load it into the corresponding module's 16-bit Capture/Compare register (PCA0CPLn and
PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transi-
tion that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge),
or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn)
in PCA0CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module is
enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt ser-
vice routine, and must be cleared by software. If both CAPPn and CAPNn bits are set to logic 1, then the
state of the Port pin associated with CEXn can be read directly to determine whether a rising-edge or fall-
ing-edge caused the capture.
Note: The CEXn input signal must remain high or low for at least two system clock cycles to be recognized by the
164
Port I/O
hardware.
Crossbar
Figure 26.4. PCA Capture Mode Diagram
CEXn
W
M
P
1
6
n
x
PCA0CPMn
C
O
M
E
n
x
C
A
P
P
n
Rev. 1.2
C
N
A
P
n
0
1
M
A
T
n
0 0 0 x
O
G
T
n
P
W
M
n
C
C
E
F
n
0
1
C
F
C
R
PCA0CN
PCA
Timebase
C
C
F
2
C
C
F
1
C
C
F
0
PCA Interrupt
Capture
PCA0CPLn
PCA0L
PCA0CPHn
PCA0H

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