IS43DR16160A-25EBLI ISSI, Integrated Silicon Solution Inc, IS43DR16160A-25EBLI Datasheet

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... Integrated Silicon Solution, Inc. — www.issi.com Rev.  B 05/24/2011 DESCRIPTION ISSI's 256Mb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. ADDRESS TABLE Parameter Configuration ...

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... FUNCTIONAL BLOCK DIAGRAM Notes: 1. An:n = no. of address pins - 1 2 ...

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... Chip Select: All commands are masked when CS is registered HIGH. CS provides for Input CS external Rank selection on systems with multiple Ranks considered part of the command code. On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is applied to each DQ, DQS, DQS, DM ODT Input signals. The ODT pin will be ignored if the EMR(1) is programmed to disable ODT. RAS, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered ...

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IS43/46DR83200A, IS43/46DR16160A Symbol  Type  Function  DQ0-7 x8 Input/ Data Input/Output: Bi-directional data bus. DQ0-15 x16 Output Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write data. The data strobes DQS(n) may be used in single ended mode or paired with optional complementary signals DQS(n) to provide differential pair signaling to the system during both reads and writes. A control bit at EMR(1)[A10] DQS, (DQS) enables or disables all complementary data strobe signals. RDQS, (RDQS Input/ DQS corresponds to the data on DQ0-DQ7 Output UDQS, (UDQS), RDQS corresponds to the Read data on DQ0-DQ7, and is enabled by EMRS LDQS, (LDQS) x16 command to EMR(1) [A11]. x16 LDQS corresponds to the data on DQ0-DQ7 UDQS corresponds to the data on DQ8-DQ15 NC No Connect: No internal electrical connection is present. VDDQ Supply DQ Power Supply: 1.8 V +/- 0.1 V VSSQ Supply DQ Ground ...

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IS43/46DR83200A, IS43/46DR16160A PIN CONFIGURATION PACKAGE CODE BALL TW-BGA (Top View) (8. 10.5 mm Body, 0.8 mm Ball Pitch Pin name Function A0 to A12 Address inputs BA0, BA1 Bank select DQ0 to DQ7 Data input/output DQS, /DQS Differential data strobe /CS Chip select /RAS, /CAS, /WE Command input CKE Clock enable CK, /CK Differential clock input DM Write data mask RDQS, /RDQS Differential Redundant Data Strobe Integrated Silicon ...

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IS43/46DR83200A, IS43/46DR16160A PIN CONFIGURATION PACKAGE CODE BALL TW-BGA (Top View) (8. 12.50 mm Body, 0.8 mm Ball Pitch Pin name Function A0 to A12 Address inputs BA0, BA1 Bank select DQ0 to DQ15 Data input/output LDQS, UDQS Differential data strobe /LDQS, /UDQS /CS Chip select /RAS, /CAS, /WE Command input CKE Clock enable CK, /CK Differential clock input LDM to UDM ...

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... Notes: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must be not greater than 0.6 x VDDQ. When VDD and VDDQ and VDDL are less than 500 mV, Vref may be equal to or less than 300 mV. 4. Voltage on any input or I/O may not exceed voltage on VDDQ. ...

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IS43/46DR83200A, IS43/46DR16160A Operating Temperature Condition Symbol Parameter TOPER Commercial Temperature Industrial Temperature, Automotive Temperature (A1) Automotive Temperature (A2) Notes Operating case temperature at center of package Operating ambient temperature immediately above package center Both temperature specifications must be met. Thermal Resistance Package Substrate (Airflow = 0m/s) 60-ball BGA 4-layer 84-ball BGA 4-layer ODT DC Electrical Characteristics PARAMETER/CONDITION  R effective impedance value for EMR(1)[A6,A2]=0,1; 75 Ω effective impedance value for EMR(1)[A6,A2]=1,0; 150 Ω effective impedance value for EMR(1)[A6,A2]=1,1; 50 Ω ...

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IS43/46DR83200A, IS43/46DR16160A Input DC logic level Symbol  Parameter VIH(dc) dc input logic HIGH VIL(dc) dc input logic LOW Input AC logic level Symbol Parameter VIH (ac) ac input logic HIGH VIL (ac) ac input logic LOW Notes: 1. Refer to Overshoot/undershoot specifications for Vpeak value: maximum peak amplitude allowed for overshoot and undershoot. AC Input Test Conditions Symbol Condition VREF Input reference voltage VSWING(MAX) Input signal maximum peak to peak swing SLEW Input signal minimum slew rate Notes: 1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the device under test. 2. The input signal minimum slew rate maintained over the range from VREF to VIH(ac) min for rising edges and the range from VREF to VIL(ac) max for falling edges as shown in the below figure timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative transitions. AC input test signal waveform V SWING(MAX) ...

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IS43/46DR83200A, IS43/46DR16160A Differential input AC Logic Level Symbol Parameter VID (ac) ac differential input voltage VIX (ac) ac differential crosspoint voltage Notes: 1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS and VCP is the complementary input signal (such DQS). The minimum value is equal to VIH(AC) - VIL(AC). 2. The typical value of VIX(AC) is expected to be about 0.5 x VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ. VIX(AC) indicates the voltage at which differential input signals must cross. 3. Refer to Overshoot/undershoot specifications for Vpeak value: maximum peak amplitude allowed for overshoot and undershoot. Differential signal levels Differential AC Output Parameters Symbol Parameter VOX (ac) ac differential crosspoint voltage Note: 1. The typical value of VOX(AC) is expected to be about 0.5 x VDDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ. VOX(AC) indicates the voltage at which differential output signals must cross. 10 Min. Max. 0.5 VDDQ 0.5 x VDDQ - 0.175 0.5 x VDDQ + 0.175 V ...

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IS43/46DR83200A, IS43/46DR16160A OVERShOOT/UNDERShOOT SPECIFICATION AC overshoot/undershoot specification for Address and Control pins Parameter Maximum peak amplitude allowed for overshoot area Maximum peak amplitude allowed for undershoot area Maximum overshoot area above VDD (see figure below) Maximum undershoot area below VSS (see figure below) Maximum Amplitude V DD Volts V SS (V) Maximum Amplitude AC overshoot and undershoot definition for address and control pins AC overshoot/undershoot specification for Clock, Data, Strobe, and Mask pins: DQ, (U/L/R) DQS, (U/L/R) DQS, DM, CK, CK Parameter Maximum peak amplitude allowed for overshoot area Maximum peak amplitude allowed for undershoot area Maximum overshoot area above VDDQ (See Figure below) Maximum undershoot area below VSSQ (See Figure below) Maximum Amplitude V DDQ Volts V SSQ (V) Maximum Amplitude AC overshoot and undershoot definition for clock, data, strobe, and mask pins Integrated Silicon ...

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... The absolute value of the slew rate as measured from equal to or greater than the slew rate as measured from AC to AC. This is guaranteed by design and characterization. 6. This represents the step size when the OCD is near 18 Ω at nominal conditions across all process corners/variations and represents only the DRAM uncertainty Ω value (no calibration) can only be achieved if the OCD impedance is 18 Ω +/-0.75 Ω under nominal conditions. 7. DRAM output slew rate specification applies to 400 MT/s, 533 MT/s & 667 MT/s speed bins. 8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQ’s is included in tDQSQ and tQHS specification. 9. DDR2 SDRAM output slew rate test load is defined in General Note 3 of the AC Timing specification Table. 12 SSTL_18 0.5 x VDDQ SSTL_18 Units Notes - 13 ...

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IS43/46DR83200A, IS43/46DR16160A IDD Specifications & Test Conditions  Conditions Symbol     IDD0 Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING IDD1 Operating one bank active-read-precharge current; IOUT = 0mA CL(IDD tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Precharge power-down current; All banks idle; IDD2P tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING IDD2Q Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; IDD2N tCK = tCK(IDD); CKE is HIGH HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Active power-down current; All banks open; IDD3P tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; ...

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IS43/46DR83200A, IS43/46DR16160A IDD Specifications & Test Conditions (continued) Conditions Symbol     IDD4R Operating burst read current; All banks open, Continuous burst reads, IOUT = 0 mA CL(IDD tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W IDD5B Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; IDD6 CK and CKE ≤ 0.2 V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING IDD7 Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA CL(IDD tRCD(IDD tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1 x tCK(IDD); CKE is HIGH HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Notes: 1. IDD specifications are tested after the device is properly initialized 2. Input slew rate is specified by AC Parametric Test Condition ...

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IS43/46DR83200A, IS43/46DR16160A IDD testing parameters Speed DDR2-800 Bin(CL-tRCD-tRP) 6-6-6 CL(IDD) 6 tRCD(IDD) 15 tRC(IDD) 60 tRRD(IDD) 7.5 tCK(IDD) 2.5 tRASmin(IDD) 45 tRASmax(IDD) 70 tRP(IDD) 15 tRFC(IDD) 75 Input/Output Capacitance: Parameter Input capacitance, CK and CK Input capacitance delta, CK and CK Input capacitance, all other input-only pins Input capacitance delta, all other input-only pins Input/output capacitance, DQ, DM, DQS, DQS Input/output capacitance delta, DQ, DM, DQS, DQS Integrated Silicon Solution, Inc. ...

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IS43/46DR83200A, IS43/46DR16160A Electrical Characteristics & AC Timing Specifications Refresh parameters (TOPER; VDDQ = 1.8 V +/- 0.1 V; VDD = 1.8 V +/- 0.1 V) Parameter Refresh to active/Refresh command time Average periodic refresh interval Notes refresh timing is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed. 2. Specified for Industrial and Automotive grade only; not applicable for Commercial grade Specified for Automotive grade (A2) only; not applicable for any other grade. T Key Timing Parameters by Speed Grade -25E Speed bin (JEDEC) DDR2-800E CL-tRCD-tRP 6-6-6 tRCD 15 tRP 15 tRC 60 tRAS 45 tCK(avg)@CL=3 5 tCK(avg)@CL=4 3.75 tCK(avg)@CL=5 3 tCK(avg)@CL=6 2.5 16 Symbol tRFC -40 ...

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IS43/46DR83200A, IS43/46DR16160A Timing Parameters by Speed Grade (DDR2-400 and DDR2-533) (For information related to the entries in this table, refer to both the Guidelines and the Specific Notes following this Table.) Parameter Clock cycle time, CL=x CK HIGH pulse width CK LOW pulse width DQS latching rising transitions to associated clock edges DQS falling edge to CK setup time DQS falling edge hold time from CK DQS input HIGH pulse width DQS input LOW pulse width Write preamble Write postamble Address and control input setup time Address and control input hold time Control & Address input pulse width for each input DQ and DM input setup time (differential strobe) DQ and DM input hold time (differential strobe) DQ and DM input setup time (single-ended strobe) DQ and DM input hold time (single-ended strobe) DQ and DM input pulse width for each input DQ output access time from CK/CK DQS output access time from CK/ CK Data-out high-impedance time from CK/ CK DQS(DQS) low-impedance time from CK low-impedance time from CK/ CK DQS-DQ skew for DQS and associated DQ signals CK half pulse width DQ hold skew factor DQ/DQS output hold time from DQS Read preamble Read postamble Integrated Silicon Solution, Inc. — ...

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IS43/46DR83200A, IS43/46DR16160A Timing Parameters by Speed Grade (DDR2-400 and DDR2-533) cont'd (For information related to the entries in this table, refer to both the Guidelines and the Specific Notes following this Table.) Parameter Active to active command period CAS to CAS command delay Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Internal read to precharge command delay tRTP CKE minimum pulse width (HIGH and LOW pulse width) Exit self refresh to a non-read command Exit self refresh to a read command Exit precharge power down to any non- read command Exit active power down to read command tXARD Exit active power down to read command (slow exit, lower power) ODT turn-on delay ODT turn-on ODT turn-on (Power-Down mode) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down mode) ODT to power down entry latency ODT power down exit latency Mode register set command cycle time MRS command to ODT update delay OCD drive mode output delay Minimum time clocks remains ON after CKE asynchronously drops LOW 18 DDR2-400 Symbol Min. ...

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IS43/46DR83200A, IS43/46DR16160A Timing Parameters by Speed Grade (DDR2-667 and DDR2-800) (For information related to the entries in this table, refer to both the Guidelines and the Specific Notes following this Table.) Parameter Average clock period Average clock HIGH pulse width Average clock LOW pulse width DQS latching rising transitions to associated clock edges DQS falling edge to CK setup time DQS falling edge hold time from CK DQS input HIGH pulse width DQS input LOW pulse width Write preamble Write postamble Address and control input setup time Address and control input hold time Control & Address input pulse width for each input DQ and DM input setup time DQ and DM input hold time DQ and DM input pulse width for each input DQ output access time from CK/CK DQS output access time from CK/CK Data-out high-impedance time from CK/CK DQS/DQS low-impedance time from CK/CK tLZ(DQS) DQ low-impedance time from CK/CK DQS-DQ skew for DQS and associated DQ signals CK half pulse width DQ hold skew factor DQ/DQS output hold time from DQS Read preamble Read postamble Integrated Silicon Solution, Inc. ...

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IS43/46DR83200A, IS43/46DR16160A Timing parameters by speed grade (DDR2-667 and DDR2-800) cont'd (For information related to the entries in this table, refer to both the Guidelines and the Specific Notes following this Table.) Parameter Activate to activate command period CAS to CAS command delay Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Internal read to precharge command delay CKE minimum pulse width (HIGH and LOW pulse width) Exit self refresh to a non-read command tXSNR Exit self refresh to a read command Exit precharge power down to any command Exit active power down to read command Exit active power down to read command (slow exit, lower power) ODT turn-on delay ODT turn-on ODT turn-on (Power-Down mode) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down mode) ODT to power down entry latency ODT Power Down Exit Latency Mode register set command cycle time OCD drive mode output delay Minimum time clocks remains ON after CKE asynchronously drops LOW 20 DDR2-667 Symbol Min. ...

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... DQS and DQS for differential strobe. 3. DDR2 SDRAM output slew rate test load Output slew rate is characterized under the test conditions as shown in Figure "Slew Rate Test Load". 4. Differential data strobe DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode, these timing VDDQ DUT DQ Output ...

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IS43/46DR83200A, IS43/46DR16160A t DQSH DQS DQS/ DQS DQS t WPRE V (ac (ac DMin Data Input (Write) Timing CK/CK CK DQS DQS/DQS DQS t RPRE DQ Data Output (Read) Timing 5. AC timings are for linear signal transitions. See Specific Notes on derating for other signal transitions. 6. All voltages are referenced to VSS. 7. These parameters guarantee device behavior, but they are not necessarily tested on each device They may be guaranteed by device design or tester correlation. 8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply ...

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IS43/46DR83200A, IS43/46DR16160A 7. Timings are specified with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS signals with a differential slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1 V/ns in single ended mode. See Specific Notes on derating for other slew rate values. 8. Data setup and hold time derating (t DtDS, DtDH derating values for DDR2-400, DDR2-553 (All units in ‘ps’; the note applies to the entire table) 4.0 V/ns 3.0 V/ns DtDS DtDH DtDS DtDH DtDS DtDH DtDS DtDH DtDS DtDH DtDS DtDH DtDS DtDH DtDS DtDH DtDS DtDH DQ 2.0 125 45 125 45 Slew 1 rate ...

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IS43/46DR83200A, IS43/46DR16160A DtDS1, DtDH1 derating values for DDR2-400, DDR2-533 (All units in ‘ps’; the note applies to the entire table) 2.0 V/ns 1.5 V/ns DtDS1 DtDH1 DtDS1 DtDH1 DtDS1 DtDH DtDS1 DtDH1 DtDS1 DtDH1 DtDS1 DtDH1 DtDS1 DtDH1 DtDS1 DtDH1 DtDS1 DtDH1 DQ 2.0 188 167 145 125 Slew 1.5 146 167 125 125 rate 1.0 63 125 42 ...

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IS43/46DR83200A, IS43/46DR16160A 9. Input Setup and Hold Time Derating (tIS, tIH) tIS, tIH Derating Values for DDR2-400, DDR2-533 DtIS 4.0 187 3.5 179 3 167 2.5 150 2.0 125 1.5 83 1.0 0 0.9 -11 Command/ 0.8 -25 Address Slew rate 0.7 -43 (V/ns) 0.6 -67 0.5 -110 0.4 -175 ...

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IS43/46DR83200A, IS43/46DR16160A DtIS and DtIH Derating Values for DDR2-667, DDR2-800 2.0 V/ns DtIS 4 150 3.5 143 3 133 2.5 120 2 100 1 Command/ 0.9 -5 Address 0.8 -13 0.7 -22 Slew rate 0.6 -34 (V/ns) 0.5 -60 0.4 -100 0.3 -168 0.25 -200 0.2 ...

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IS43/46DR83200A, IS43/46DR16160A 10. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 11. MIN ( tCL, tCH) refers to the smaller of the actual clock LOW time and the actual clock HIGH time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). For example, tCL and tCH are = 50% of the period, less the half period jitter ( tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk ( tJIT(crosstalk)) into the clock traces. 12. tQH = tHP – tQHS, where minimum half clock period for any given cycle and is defined by clock HIGH or clock LOW (tCH, tCL). tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one transition followed by the worst case pull- the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. 13. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate mismatch between DQS / DQS and associated DQ in any given cycle. 14. tDAL = WR + RU{ tRP[ns] / tCK[ns] }, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For DDR533 at tCK = 3.75ns with WR programmed to 4 clocks. tDAL = 3.75 ns) clocks = 4 + (4) clocks = 8 clocks. 15. The clock frequency is allowed to change during self–refresh mode or precharge power-down mode. In case of clock frequency change during precharge power-down, a specific procedure is required as described in section 3.13. 16. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-400/533, tAOND ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns. For DDR2-667/800, tAOND is 2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges. 17. ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD, which is interpreted differently per speed bin. For ...

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... These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal ((L/U/R)DQS/ DQS) crossing. 32. For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK(avg)}, which is in clock cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK(avg)}, which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR2-667 5-5-5, of which tRP = 15ns, the device will support tnRP = RU{tRP / tCK(avg ...

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IS43/46DR83200A, IS43/46DR16160A 33. tDAL [nCK [nCK] + tnRP [nCK {tRP [ps] / tCK(avg) [ps] }, where WR is the value programmed in the mode register set. 34. New units, ‘tCK(avg)’ and ‘nCK’, are introduced in DDR2-667 and DDR2-800. Unit ‘tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ‘nCK’ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and DDR2-533, ‘tCK’ is used for both concepts. ex) tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm+2, even if (Tm tCK(avg) + tERR(2per),min. 35. Input clock jitter spec parameter. These parameters and the ones in the table below are referred to as 'input clock jitter spec parameters' and these parameters apply to DDR2-667 and DDR2-800 only. The jitter specified is a random jitter meeting a Gaussian distribution. Parameter Clock period jitter Clock period jitter during DLL locking period Cycle to cycle clock period jitter Cycle to cycle clock period jitter during DLL locking period Cumulative error across 2 cycles Cumulative error across 3 cycles Cumulative error across 4 cycles Cumulative error across 5 cycles Cumulative error across n cycles ... 10, inclusive Cumulative error across n cycles ... 50, inclusive Duty cycle jitter Integrated Silicon Solution, Inc. — www.issi.com Rev.  B ...

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... When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6- 10per) of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tERR(6-10per),min = - 272 ps and tERR(6-10per), max = + 293 ps, then tDQSCK,min(derated) = tDQSCK,min - tERR(6-10per),max = - 400 ps - 293 693 ps and tDQSCK,max(derated) = tDQSCK,max - tERR(6-10per),min = 400 ps + 272 672 ps. Similarly, tLZ(DQ) for DDR2-667 derates to tLZ(DQ),min(derated 900 ps - 293 1193 ps and tLZ(DQ),max(derated) = 450 ps + 272 722 ps ...

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... For tAOFD of DDR2-400/533, the 1/2 clock of tCK in the 2.5 x tCK assumes a tCH, input clock HIGH pulse width of 0.5 relative to tCK. tAOF,min and tAOF,max should each be derated by the same amount as the actual amount of tCH offset present at the DRAM input with respect to 0.5. For example input clock has a worst case tCH of 0.45, the tAOF,min should be derated by subtracting 0.05 x tCK from it, whereas if an input clock has a worst case tCH of 0.55, the tAOF,max should be derated by adding 0.05 x tCK to it. Therefore, we have; ...

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... - Apply VDD/VDDL before or at the same time as VDDQ. - VDD/VDDL voltage ramp time must be no greater than 200ms from when VDD ramps from 300mV to VDD min - Apply VDDQ before or at the same time as VTT. - The VDDQ voltage ramp time from when VDD min is achieved on VDD to when VDDQ min is achieved on VDDQ must be no greater than 500ms. (Note: While VDD is ramping, current may be supplied from VDD through the DRAM to VDDQ.) - VREF must track VDDQ/2, VREF must be within +/- 300mv with respect to VDDQ/2 during supply ramp time. - VDDQ ≥ VREF must be met at all times. - Apply VTT. - The VTT voltage ramp time from when VDDQ min is achieved on VDDQ to when VTT min is achieved on VTT must be no greater than 500ms. ...

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... If OCD calibration is not used, EMRS to EMR(1) to set OCD Calibration Default (A9=A8=A7=HIGH) followed by EMRS to EMR(1) to exit OCD Calibration Mode (A9=A8=A7=LOW) must be issued with other operating parameters of EMR(1). m) The DDR2 SDRAM is now ready for normal operation. tCH tCL CK /CK tIS CKE ODT PRE Command ...

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... CAS, WE, BA0 and BA1, while controlling the state of address pins A0 - A12. The DDR2 SDRAM should be in all bank precharge state with CKE already HIGH prior to writing into the mode register. The mode register set command cycle time (tMRD) is required to complete the write operation to the mode register. The mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. The mode register is divided into various fields depending on functionality. Burst length is defined with options of 4 and 8 bit burst lengths. The burst length decodes are compatible with DDR SDRAM. Burst address sequence type is defined by A3, CAS latency is defined A6. The DDR2 does not support half clock latency mode mode bit and must be set to LOW for normal MRS operation used for DLL reset. Write recovery time WR is defined A11. Refer to the table for specific codes. 34 Integrated Silicon Solution, Inc. — ...

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... IS43/46DR83200A, IS43/46DR16160A DDR2 SDRAM Mode Register Set (MRS) A12 Address Mode Field Register BA1 0 0 BA0 A11 A12 PD A11 A10 DLL CAS A5 Latency Burst A1 Length A0 Notes: 1. For DDR2-400/533, WR (write recovery for autoprecharge) min is determined by tCK max and WR max is determined by tCK min clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up to the next integer (WR[cycles] = RU{ tWR[ns] / tCK[ns] }, where RU stands for round up) ...

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... Stop command is not supported on DDR2 SDRAM devices. Burst Length and Sequence Burst Length Starting Address (A1, A0 ...

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... The EMR(1) stores the data for enabling or disabling the DLL, output driver strength, additive latency, ODT, DQS disable, OCD program, RDQS enable. The default value of the EMR(1) is not defined, therefore the extended mode register must be programmed during initialization for proper operation. The EMR(1) is written by asserting LOW on CS, RAS, CAS, WE, HIGH on BA0 and LOW on BA1, while controlling the states of address pins A0 - A12. The DDR2 SDRAM should be in all bank precharge with CKE already HIGH prior to writing into the extended mode register. The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register. Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. ...

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IS43/46DR83200A, IS43/46DR16160A A12 0 Address Mode Field Register 1 BA1 0 BA0 1 A11 0 A12 Qff 1 A10 *1 A11 RDQS 0 1 A10 /DQS OCD A8 Program Rtt A5 ...

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... Extended Mode Register 2 (EMR2) The Extended Mode Register 2 controls refresh related features. The default value of the EMR(2) is not defined, therefore the mode register must be programmed during initialization for proper operation. The EMR(2) is written by asserting LOW on CS, RAS, CAS, WE, HIGH on BA1 and LOW on BA0, while controlling the states of address pins A0 - A12. The DDR2 SDRAM should be in all bank precharge state with CKE already HIGH prior to writing into the EMR(2). The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the EMR(2). Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. ...

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... IS43/46DR83200A, IS43/46DR16160A DDR2 SDRAM Extended Mode Register 3 (EMR3) No function is defined in Extended Mode Register (3). The default value of the EMR(3) is not defined, therefore the EMR(3) must be programmed during initialization for proper operation. All bits in EMR(3) except BA0 and BA1 are reserved for future use and must be set to 0 when programming this mode register. Address Field BA1 BA0 A12 A11 Mode Register A10 Integrated Silicon Solution, Inc. — www.issi.com Rev.  B ...

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... L Power Down Exit L H Notes: 1. All DDR2 SDRAM commands are defined by states of CS, RAS, CAS , WE and CKE at the rising edge of the clock. 2. Bank addresses BA0, BA1 (BA) determine which bank operated upon. For (E)MRS BA selects an (Extended) Mode Register. 3. Burst reads or writes at BL=4 cannot be terminated or interrupted. See sections "Reads interrupted by a Read" and "Writes interrupted by a Write" for details. 4. The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh requirements 5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. See section 3.4.4. ...

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... H Idle H H Notes: 1. CKE (N) is the logic state of CKE at clock edge N; CKE (N–1) was the state of CKE at the previous clock edge. 2. Current state is the state of the DDR2 SDRAM immediately prior to clock edge N. 3. COMMAND (N) is the command registered at clock edge N, and ACTION ( result of COMMAND (N). 4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period. Read commands may be issued only after tXSRD (200 clocks) is satisfied. 6. Self Refresh mode can only be entered from the All Banks Idle state. 7. Must be a legal command as defined in the Command Truth Table. ...

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... The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst; if auto precharge is not selected, the row will remain open for subsequent accesses. DDR2 SDRAM also supports the AL feature, which allows a READ or WRITE command to be issued prior to tRCD (MIN) by delaying the actual registration of the READ/WRITE command to the internal device by AL clock cycles. Input data appearing on the DQ is written to the memory array subject to the DM input logic level appearing coincident with the data given DM signal is registered LOW, the corresponding data will be written to memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location ...

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... The On-Die Termination feature allows the DDR2 SDRAM to easily implement a termination resistance (Rtt) for each DQ, DQS, DQS, RDQS, and RDQS signal. The ODT feature can be configured with the Extended Mode Register Set (EMRS) command, and turned on or off using the ODT input signal. Before and after the EMRS is issued, the ODT input must be received with respect to the timings of tAOFD, tMOD(max), tAOND; and the CKE input must be held HIGH throughout the duration of tMOD(max). The DDR2 SDRAM supports the ODT on and off functionality in Active, Standby, and Power Down modes, but not in Self Refresh mode. ODT timing diagrams follow for Active/Standby mode and Power Down mode. EMRS to ODT Update Delay CMD E MRS ...

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IS43/46DR83200A, IS43/46DR16160A ODT On/Off Timing for Active/Standby mode CKE (ac) ODT IH t AOND ODT On/Off Timing for Power-Down mode CKE ODT (ac) ...

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... IS43DR83200A-37CBI IS43DR83200A-37CBLI C  o 6-6-6 IS43DR16160A-25EBL 5-5-5 IS43DR16160A-3DBL 4-4-4 IS43DR16160A-37CBL C, T  = -40 C to +85 C   6-6-6 IS43DR16160A-25EBLI 5-5-5 IS43DR16160A-3DBLI IS43DR16160A-3DBI 4-4-4 IS43DR16160A-37CBLI 3-3-3 IS43DR16160A-5BBLI C to +95 C, T  = -40 C to + 4-4-4 IS46DR16160A-37CBLA1 IS46DR16160A-37CBA1 3-3-3 IS46DR16160A-5BBLA1 C  ...

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IS43/46DR83200A, IS43/46DR16160A Integrated Silicon Solution, Inc. — www.issi.com Rev.  B 05/24/2011 47 ...

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IS43/46DR83200A, IS43/46DR16160A 48 Integrated Silicon Solution, Inc. — www.issi.com Rev.  B 05/24/2011 ...