LMC567CM/NOPB National Semiconductor, LMC567CM/NOPB Datasheet - Page 5

• Manufacturer Part Number: LMC567CM/NOPB
• Description: IC TONE DECODER CMOS 8-SOIC
• Manufacturer: National Semiconductor
• Series: LMCMOS™r

Specifications of LMC567CM/NOPB

• Function: Tone Decoder
• Number Of Circuits: 1
• Voltage - Supply: 2 V ~ 9 V
• Power (watts): 500mW
• Operating Temperature: -25°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Includes: Low Supply Current Drain, Noise Rejected, Out-of-Band Signals
• Operating Frequency (max): 500kHz
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Supply Voltage (min): 2V
• Operating Supply Voltage (max): 9V
• Operating Temp Range: -25C to 125C
• Operating Temperature Classification: Commercial
• Package Type: SOIC N
• Mounting: Surface Mount
• Pin Count: 8
• Supply Current: 0.8mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Interface: -
• Lead Free Status / Rohs Status: Compliant
• Other names: *LMC567CM/NOPB

Applications Information
Diagram)
GENERAL
The LMC567 low power tone decoder can be operated at
supply voltages of 2V to 9V and at input frequencies ranging
from 1 Hz up to 500 kHz.
The LMC567 can be directly substituted in most LM567
applications with the following provisions:
1. Oscillator timing capacitor Ct must be halved to double
2. Filter capacitors C1 and C2 must be reduced by a factor
3. The output current demanded of pin 8 must be limited to
OSCILLATOR TIMING COMPONENTS
The voltage-controlled oscillator (VCO) on the LMC567 must
be set up to run at twice the frequency of the input signal
tone to be decoded. The center frequency of the VCO is set
by timing resistor Rt and timing capacitor Ct connected to
pins 5 and 6 of the IC. The center frequency as a function of
Rt and Ct is given by:
Since this will cause an input tone of half F
This equation is accurate at low frequencies; however,
above 50 kHz (F
actual frequency to be lower than predicted.
The choice of Rt and Ct will be a tradeoff between supply
current and practical capacitor values. An additional supply
current component is introduced due to Rt being switched to
V
Thus the supply current can be minimized by keeping Rt as
large as possible (see supply current vs. operating fre-
quency curves). However, the desired frequency will dictate
an RtCt product such that increasing Rt will require a smaller
Ct. Below Ct = 100 pF, circuit board stray capacitances begin
to play a role in determining the oscillation frequency which
ultimately limits the minimum Ct.
To allow for I.C. and component value tolerances, the oscil-
lator timing components will require a trim. This is generally
accomplished by using a variable resistor as part of Rt,
although Ct could also be padded. The amount of initial
frequency variation due to the LMC567 itself is given in the
electrical specifications; the total trim range must also ac-
commodate the tolerances of Rt and Ct.
s
every half cycle to charge Ct:
the oscillator frequency relative to the input frequency
(See OSCILLATOR TIMING COMPONENTS).
of 8 to maintain the same filter time constants.
the specified capability of the LMC567.
osc
I
s
due to Rt = V
= 100 kHz), internal delays cause the
s
/(4Rt)
osc
(refer to Block
to be decoded,
5
SUPPLY DECOUPLING
The decoupling of supply pin 4 becomes more critical at high
supply voltages with high operating frequencies, requiring
C4 to be placed as close as possible to pin 4.
INPUT PIN
The input pin 3 is internally ground-referenced with a nomi-
nal 40 kΩ resistor. Signals which are already centered on 0V
may be directly coupled to pin 3; however, any d.c. potential
must be isolated via a coupling capacitor. Inputs of multiple
LMC567 devices can be paralleled without individual d.c.
isolation.
LOOP FILTER
Pin 2 is the combined output of the phase detector and
control input of the VCO for the phase-locked loop (PLL).
Capacitor C2 in conjunction with the nominal 80 kΩ pin 2
internal resistance forms the loop filter.
For small values of C2, the PLL will have a fast acquisition
time and the pull-in range will be set by the built in VCO
frequency stops, which also determine the largest detection
bandwidth (LDBW). Increasing C2 results in improved noise
immunity at the expense of acquisition time, and the pull-in
range will begin to become narrower than the LDBW (see
Bandwidth as a Function of C2 curve). However, the maxi-
mum hold-in range will always equal the LDBW.
OUTPUT FILTER
Pin 1 is the output of a negative-going amplitude detector
which has a nominal 0 signal output of 7/9 V
is locked to the input, an increase in signal level causes the
detector output to move negative. When pin 1 reaches
2/3 V
Capacitor C1 in conjunction with the nominal 40 kΩ pin 1
internal resistance forms the output filter. The size of C1 is a
tradeoff between slew rate and carrier ripple at the output
comparator. Low values of C1 produce the least delay be-
tween the input and output for tone burst applications, while
larger values of C1 improve noise immunity.
Pin 1 also provides a means for shifting the input threshold
higher or lower by connecting an external resistor to supply
or ground. However, reducing the threshold using this tech-
nique increases sensitivity to pin 1 carrier ripple and also
results in more part to part threshold variation.
OUTPUT PIN
The output at pin 8 is an N-channel FET switch to ground
which is activated when the PLL is locked and the input tone
is of sufficient amplitude to cause pin 1 to fall below 2/3 V
Apart from the obvious current component due to the exter-
nal pin 8 load resistor, no additional supply current is re-
quired to activate the switch. The on resistance of the switch
is inversely proportional to supply; thus the “sat” voltage for
a given output current will increase at lower supplies.
s
the output is activated (see OUTPUT PIN).
s
. When the PLL
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s
.