DS21352L+ Maxim Integrated Products, DS21352L+ Datasheet - Page 31
DS21352L+
Manufacturer Part Number
DS21352L+
Description
IC TXRX T1 1-CHIP 3.3V 100-LQFP
Manufacturer
Maxim Integrated Products
Datasheet
1.DS21352L.pdf
(137 pages)
Specifications of DS21352L+
Function
Single-Chip Transceiver
Interface
HDLC, T1
Number Of Circuits
1
Voltage - Supply
3.14 V ~ 3.47 V
Current - Supply
75mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-LQFP
Includes
DSX-1 and CSU Line Build-Out Generator, HDLC Controller, In-Band Loop Code Generator and Detector
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
- Current page: 31 of 137
- Download datasheet (2Mb)
Table 6-1 DEVICE ID BIT MAP
DS2152
DS21352
DS21552
DS2154
DS21354
DS21554
The lower four bits of the IDR are used to display the die revision of the chip.
RCR1: RECEIVE CONTROL REGISTER 1 (Address=2B Hex)
(MSB)
LCVCRF
SYMBOL
LCVCRF
RESYNC
SYNCC
SYNCT
SYNCE
OOF1
OOF2
ARC
SCT
POSITION
ARC
RCR1.0
RCR1.7
RCR1.6
RCR1.5
RCR1.4
RCR1.3
RCR1.2
RCR1.1
T1/E1
0
0
0
1
1
1
OOF1
NAME AND DESCRIPTION
Line Code Violation Count Register Function Select.
0 = do not count excessive zeros
1 = count excessive zeros
Auto Resync Criteria.
0 = Resync on OOF or RCL event
1 = Resync on OOF only
Out Of Frame Select 1.
0 = 2/4 frame bits in error
1 = 2/5 frame bits in error
Out Of Frame Select 2.
0 = follow RCR1.5
1 = 2/6 frame bits in error
Sync Criteria.
In D4 Framing Mode.
0 = search for Ft pattern, then search for Fs pattern
1 = cross couple Ft and Fs pattern
In ESF Framing Mode.
0 = search for FPS pattern only
1 = search for FPS and verify with CRC6
Sync Time.
0 = qualify 10 bits
1 = qualify 24 bits
Sync Enable.
0 = auto resync enabled
1 = auto resync disabled
Resync. When toggled from low to high, a resynchronization of the receive side framer
is initiated. Must be cleared and set again for a subsequent resync.
OOF2
Bit 6
0
0
0
0
0
0
31 of 137
SYNCC
Bit 5
0
0
1
0
0
1
SYNCT
SYNCE
Bit 4
0
1
0
0
1
0
DS21352/DS21552
RESYNC
(LSB)
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