DS3171N+ Maxim Integrated Products, DS3171N+ Datasheet - Page 135

• Manufacturer Part Number: DS3171N+
• Description: TXRX SGL DS3/E3 400PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3171N+

• Function: Single-Chip Transceiver
• Interface: DS3, E3
• Number Of Circuits: 1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 273mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Includes: DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: 90-31710+N00

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 14 to 12: Payload AIS Select [2:0] (PAIS[2:0]). This bit controls when an unframed all ones signal is forced
on the receive data path after the receive framer and payload loopback mux. Default: Payload AIS always sent.
See
Bits 11 to 10: Line AIS Select [1:0] (LAIS[1:0). These bits control when a DS3 framed AIS or an unframed all
ones signal is to be transmitted on TPOSn/TNEGn and/or TXPn/TXNn. The signal on TPOSn/TNEGn can be AMI
or unipolar. This signal is sent even when in diagnostic loopback and always over-rides signals from the framers.
Default: AIS sent if DLB is enabled. See
Bit 9: BERT Enable (BENA). This bit is used to enable the BERT logic. The BERT pattern will be the payload data
replacing the data from the TSERn pin.
Bit 7: Transmit Manual Error Insert (TMEI) This bit is used to insert errors in all error insertion logic configured to
use this bit when PORT.CR1.MEIM=0. The error(s) will be inserted when this bit is toggled low to high.
Bit 6: Transmit Manual Error Insert Mode (MEIM). These bits select the method transmit manual error insertion
for this port for error generators configured to use the external TMEI signal. The global updates are controlled by
the GL.CR1.MEIMS bit.
Bit 4: Performance Monitor Update Mode (PMUM). These bits select the method of updating the performance
monitor registers. The global updates are controlled by the GL.CR1.GPM[1:0] bits.
Bit 3: Performance Monitor Register Update (PMU) This bit is used to update all of the performance monitor
registers configured to use this bit when PORT.CR1.PMUM=0. The performance registers configured to use this
signal will be updated with the latest count value and the counters reset when this bit is toggled low to high. The bit
should remain high until the performance register update status bit (PORT.SR.PMS) goes high, then it should be
brought back low which clears the PMS status bit.
Bit 2: Power-Down (PD). When this bit is set, the LIU and digital logic for this port are powered down and
considered “out of service.” The logic is powered down by stopping the clocks. See the
section in Section 10.3.
Bit 1: Reset Data Path (RSTDP). When this bit is set, it will force all of the internal data path registers in this port
to their default state. This bit must be set high for a minimum of 100ns and then set back low. See the
Power-Down
this bit will be set to one).
Bit 0: Reset (RST). When this bit is set, it will force all the internal data path and status and control registers
(except this RST bit) of this port to their default state. See the
Table
0 = BERT logic disabled and powered down
1 = BERT logic enabled
0 = Port software update via PORT.CR1.TMEI
1 = Global update source
0 = Port software update
1 = Global update
0 = Normal operation
1 = Power-down port circuits (default state)
0 = Normal operation
1 = Force all data path registers to their default values
10-19.
RESERVED
section in Section 10.3. Note: The Default State of this bit is 1 (after a general reset (port or global),
TMEI
15
0
7
0
PAIS2
MEIM
14
0
6
0
PORT.CR1
Port Control Register 1
(0,2,4,6)40h
PAIS1
Table
13
--
--
0
5
10-18.
PMUM
PAIS0
12
0
0
4
135
Reset and Power-Down
LAIS1
PMU
11
0
3
0
LAIS0
PD
10
0
2
1
section in Section 10.3. This
Reset and Power-Down
RSTDP
BENA
9
0
1
1
RESERVED
Reset and
RST
8
0
0
0