DS3171N+ Maxim Integrated Products, DS3171N+ Datasheet - Page 66

• Manufacturer Part Number: DS3171N+
• Description: TXRX SGL DS3/E3 400PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3171N+

• Function: Single-Chip Transceiver
• Interface: DS3, E3
• Number Of Circuits: 1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 273mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Includes: DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: 90-31710+N00

10.4.3 One Second Reference Generation
The one-second-reference signal is used as an option to update the performance registers on a precise one-
second interval. The generated internal signal should be about 50% duty cycle and it is derived from the Global 8
kHz reference signal by dividing it by 8000. The low to high edge on this signal will set the GL.SRL.ONESL latched
one second detect bit which can generate an interrupt when the GL.SRIE.ONESIE interrupt enable bit is set. The
low to high edge can also be used to generate performance monitor updates when GL.CR1.GPM[1:0]=1X.
10.4.4 General-Purpose IO Pins
There are eight general-purpose IO pins that can be used for general IO, global signals and per port alarm signals.
Each pin is independently configurable to be a general-purpose input, general-purpose output, global signal or port
alarm. Two of the GPIO pins are assigned to each port and can be programmed to output one or two alarm
statuses using one or two GPIO pins. One of the two pins assigned to each port can be programmed as global
input or output signals. When the device is bonded out (or has ports powered down) to have 1, 2 or 3 ports active,
the GPIO pins associated with the disabled ports will still operate as either general-purpose inputs, general-
purpose outputs or global signals. When the ports are disabled and GL.GIOCR.GPIOx[1:0] = 01, the GPIO pin will
be an output driving low. The 8KREFI, TMEI, and PMU signals that can be sourced by the GPIO pin will be driven
low into the core logic when the GPIO pin is not selected for the source of the signal.
Table 10-14
Table 10-14. GPIO Global Signals
Pin
GPIO2
GPIO4
GPIO6
GPIO8
Table 10-15
Table 10-15. GPIO Pin Global Mode Select Bits
GL.GIOCR.GPIOnSx
Table 10-16
located in the
n = port 1 to 4, x = A or B, valid when a GPIO pin is not selected for a global signal
Global signal
8KREFO output
8KREFI input
TMEI input
PMU input
00
01
10
11
lists the purpose and control thereof of the General-Purpose IO Pins.
describes the selection of mode for the GPIO Pins.
lists the various port alarm monitors that can be output on the GPIO pins. The GPIO(A/B)[3:0] bits are
PORT.CR4
Register.
GPIO pin mode
Input
Port alarm status selected by port
GPIO
Output logic 0
Output logic 1
Control bit
GL.CR2.G8KOS
GL.CR2.G8KIS
GL.CR1.MEIMS
GL.CR1.GPM[1:0]
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