PEF 20954 HT V1.1 Infineon Technologies, PEF 20954 HT V1.1 Datasheet - Page 160
PEF 20954 HT V1.1
Manufacturer Part Number
PEF 20954 HT V1.1
Description
IC ECHO CANCELLER DGTL TQFP144
Manufacturer
Infineon Technologies
Datasheet
1.PEB_20954_HT_V1.1.pdf
(164 pages)
Specifications of PEF 20954 HT V1.1
Function
Smart Integrated Digital Echo Canceller (SIDEC)
Interface
PCM, Serial, UCC
Number Of Circuits
1
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
350mA
Power (watts)
900mW
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
144-LFQFP
Includes
Double Talk Detection
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
PEF20954HTV1.1
SP000007505
SP000007505
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Figure 50
echo path
The transmission path between R
to describe the signal path of the echo.
echo path capacity
The maximum echo path delay for which an echo canceller is designed to operate.
echo path delay (t
The delay from the Rout port to the Sin port due to the delays inherent in the echo path
transmission facilities including dispersion time due to the network elements. In case of
multiple echo paths, all delays and dispersions of any individual echo path are included.
The dispersion time, which varies with different networks, is required to accommodate
the band-limiting, and hybrid transit effects.
echo return loss (ERL) (A
The attenuation of a signal from the receive-out port (R
echo canceller, due to transmission and hybrid loss, i.e. the loss in the (near-end) echo
path.
Data Sheet
Near-end
Hybrid
Location of levels and loss of an echo canceller
Elements
Network
Elements
Network
d
)
A
ECHO
ECHO
S
R
in
out
)
out
and S
other control circuitry
Echo estimator and
160
Digital Subtractor
in
of an echo canceller. This term is intended
A
CANC
Receive path
Send path
out
) to the send-in port (S
Non-linear
processor
A
L
NLP
RES
T1524860-96
Rev. 2, 2004-07-28
PEB 20954
PEF 20954
S
R
Glossary
out
Far-end
in
L
L
in
Rin
RET
) of an
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